Nonvolatile semiconductor memory device having data line dedicat

Details Nonvolatile semiconductor memory device having data line dedicat Nonvolatile semiconductor memory device having data line dedicat

1997-05-07

1999-04-20

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular biasing

36518512, 36518905, G11C 700

Patent

active

058963170

ABSTRACT:
It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.

REFERENCES:
patent: 5541879 (1996-07-01), Suh et al.
patent: 5712818 (1998-01-01), Lee et al.

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