Static information storage and retrieval – Addressing
Reexamination Certificate
2001-11-28
2003-04-22
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
C365S210130, C365S200000, C365S238500
Reexamination Certificate
active
06552950
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor device capable of freely accessing memory cell arrays irrespective of physical addresses of the memory cell arrays and a method thereof.
2. Description of Related Art
It is well known that nonvolatile semiconductor memory devices can permanently store data in memory cells when an external power goes off, and that such devices are typically used in applications for mask read only memory (MROM), programmable read only memory (PROM), erasable and programmable read only memory (EPROM) and electrically erasable and programmable read only memory (EEPROM).
With MROMs, PROMs or EPROMs, users cannot easily erase or reprogram stored data because the erasing or reprogramming of the stored data is performed on the board of the memory device. However, with EEPROMs, users can readily perform an erase or reprogramming operation, because the EEPROM can be electrically erased and reprogrammed repeatedly through the application of higher than normal electrical voltage. Therefore, EPROMs are used in numerous applications, such as system program storage devices or auxiliary memory devices requiring frequent data renewal. For instance, EEPROMs having a more compact size and capable of operating at high speed are typically required in various applications such as electronic devices controlled by computers or microprocessors, or in a battery powered computer system such as a portable or laptop computer system.
Flash EEPROMs are largely classified into a NAND type, NOR type or AND type EEPROM depending on how memory cells are connected to bit lines. The NAND type EEPROM can be integrated at higher density than the NOR or AND type, because the number of select transistors per cell and the number of holes contacted with bit lines can be reduced in the NAND type. An example of a NAND type flash EEPROM is disclosed in an article entitled “NEW DEVICE TECHNOLOGIES FOR 5V-ONLY 4 Mb EEPROM WITH NAND STRUCTURE CELL” of IEDN, pp. 412 to 415, 1988. Further, an improved device, in which NAND cell units are formed on a P type well region of an N type semiconductor substrate, and a method for erasing and programming the device are disclosed an article entitled “A NAND STRUCTURED CELL WITH A NEW PROGRAMMING TECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY FLASH EEPROM” of “symposium on VLSI Technology”, pp. 129-130, 1990. Such NAND type Flash EEPROM can be advantageously applied at a large scaled sub-memory device because of its high density.
In the NAND flash EEPROM memory cells, N-type source and drain regions are spaced on a P-type substrate. A floating gate and a control gate, which are separated by an insulating layer, are sequentially formed on a channel region formed between the source and drain regions. Program data are accumulated in the conductive floating gate (FG) in response to a program voltage applied to the control gate (CG).
The NAND type flash EEPROM has erase, write and read operations. The erase and write operations are performed by using F-N tunneling current. During the erase operation, a high voltage Vsub is applied to a substrate and a low voltage is applied to a control gate (CG). At this time, a voltage Vfg, which is determined in response to the ratio of the capacitance between the CG and FG and the capacitance between the FG and the substrate, is applied to the FG. When the potential difference between the floating gate voltage Vfg and the substrate voltage Vsub is larger than the voltage for producing the F-N tunneling, electrons accumulated in the FG flow to the substrate. As a result, a threshold voltage Vt of the memory cell transistor will drop, and the erase operation is performed. In the erase operation, 0V is applied to the CG and the source region and a voltage for producing current flowing through therein is applied to the drain region. The erased cell may be said to be storing a logic “1”. In the write operation, 0V is applied to the source and drain regions and a high voltage is applied to the CG. At this time, an inversion layer is formed in the channel region and the source and drain regions have a potential of 0V.
When the potential difference between Vfg and Vchannel (0V) is large enough to produce an F-N tunneling, electrons flow from the channel region to the FG. In this case, the Vt increases and a program operation is performed. In the program operation, a predetermined voltage is applied to the CG, 0V is applied to the source region, and a proper voltage is applied to the drain region, but current does not flow through the drain. The programmed cell may be said to be storing a logic “0”.
In the NAND type flash memory, a unit of a memory cell array comprises a first select transistor, a second select transistor, and a cell string having a plurality of memory cell transistors in which drain-source channels are connected in serial with each other and FGs are formed between the first and second transistors. The cell string may be called a NAND cell unit. In addition to the memory cell array, the NAND type flash memory comprises bit lines for inputting/receiving data to/from the cell strings, word lines crossed with the bit lines for controlling gates of the memory cell transistors and the select transistors, a X decoder for selecting the word lines, page buffers connected to the bit lines to sense and store input/output data of the memory cell transistors, and a Y decoder circuit for controlling data input/output to/from the page buffers.
In the memory cell array, a page unit comprises all the memory cell transistors whose control gates commonly connected to one word line. A cell block comprises a plurality of pages, a unit of cell block generally comprises one or a plurality of cell strings per bit line.
As described above, the NAND type flash memory generally performs a read operation and a program operation by a page unit and an erase operation by a cell block unit. Practically, electrons flowing between the FG and the channel of the memory cell transistor only occurs in the erase operation and the program operation.
In a read operation, after the erase operation and the program operation, data stored in the memory cell transistors are read without damaging the stored data. In the read operation, a non-selected CG receives a higher voltage than a selected CG. As a result, a current flowing on a corresponding bit line depends on the programmed state of the selected memory cell transistor. If a threshold voltage of the programmed memory cell is higher than a reference voltage, the memory cell is an “off-cell” and a corresponding bit line is charged with a high voltage. In contrast, if the threshold voltage of the programmed memory cell is lower than a reference voltage, the memory cell is an “on-cell”, and the corresponding bit line is discharged with a low voltage. A sense amplifier, called as a page buffer, determines the state of a bit line as “0” or “1”.
In this case, since the number of cell strings coupled to one bit line is large, the amount of loading on the bit line is large and the amount of current flowing through the “on-cell” during sensing the “on-cell” is small. Accordingly, the time for developing voltage and the time for sensing the “on-cell” should be relatively long. Thus, the time for reading data is long and a read operation is slow. To solve the problem, the NAND type flash memory performs the read operation by a page unit for serial access operation, in which all data in one page are read at one time and the results are output in serial. As a result, when the amounts of data are large, the reading time per one bit is likely reduced and the sensing time can be reduced.
One page of the memory cell array comprises a page of main memory array and a page of spare memory array. The main memory array stores general information and the spare memory array stores error correction codes and page information.
There are a main sequential read operation mode, a spare sequential read operation mode, and a whole pa
Cho Tae-Hee
Lee Yeong-Taek
F. Chau & Associates LLP
Le Thong
Nelms David
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