Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2006-04-27
2008-10-07
Phan, Trong (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170, C365S185250, C365S063000, C365S203000, C365S230030
Reexamination Certificate
active
07433230
ABSTRACT:
In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.
REFERENCES:
patent: 5274597 (1993-12-01), Ohbayashi et al.
patent: 5748545 (1998-05-01), Lee et al.
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5917745 (1999-06-01), Fujii
patent: 5973983 (1999-10-01), Hidaka
patent: 5991223 (1999-11-01), Kozaru et al.
patent: 6002633 (1999-12-01), Oppold et al.
patent: 6088286 (2000-07-01), Yamauchi et al.
patent: 6147925 (2000-11-01), Tomishima et al.
patent: 6157584 (2000-12-01), Holst
patent: 6157588 (2000-12-01), Matsumoto et al.
patent: 6304509 (2001-10-01), Hirobe et al.
patent: 6442078 (2002-08-01), Arimoto
patent: 6496430 (2002-12-01), Aikawa et al.
patent: 6512719 (2003-01-01), Fujisawa et al.
patent: 6542428 (2003-04-01), Hidaka
patent: 6545931 (2003-04-01), Hidaka
patent: 6545934 (2003-04-01), Yamashita et al.
patent: 6643182 (2003-11-01), Yanagisawa et al.
patent: 6678195 (2004-01-01), Hidaka
patent: 6781879 (2004-08-01), Tanzawa et al.
patent: 6847578 (2005-01-01), Ayukawa et al.
patent: 6891755 (2005-05-01), Silvagni et al.
patent: 7239571 (2007-07-01), Tanaka
patent: 7242627 (2007-07-01), Mizuno et al.
Kurata, H, et al.: “Self-Boosted Charge Injection for 90-nm-Node 4-Gb Multilevel AG-AND Flash Memories Programmable at 16 MB/s,” 2004 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 72-73.
Iga Hironori
Kono Takashi
Kunori Yuichi
McDermott Will & Emery LLP
Phan Trong
Renesas Technology Corp.
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