Nonvolatile semiconductor memory device having adjacent memory c

Details Nonvolatile semiconductor memory device having adjacent memory c Nonvolatile semiconductor memory device having adjacent memory c

1993-01-14

1994-08-09

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

257315, 257316, 257319, 257344, 257408, G11C 1134, G11C 1140

Patent

active

053372743

ABSTRACT:
The drain region of a memory cell transistor is constituted of a drain diffusion layer and a p.sup.- diffusion layer to provide a steep gradient of the impurity concentration. The source region of the memory cell transistor is constituted of a source diffusion layer and an n.sup.- diffusion layer to provide a gentle gradient of the impurity concentration. The LDD structure is employed in the source and drain regions of a peripheral transistor.

REFERENCES:
patent: 4928156 (1990-05-01), Alvis
patent: 4939558 (1990-07-01), Smayling
patent: 5032881 (1991-07-01), Sardo
patent: 5124780 (1992-06-01), Sandhu
patent: 5210436 (1993-05-01), Kakizoe
patent: 5234850 (1993-08-01), Liao
patent: 5257095 (1993-10-01), Liu

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