Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-02-28
2002-12-17
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185220, C365S185280
Reexamination Certificate
active
06496412
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-266085, filed Sep. 20, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor memory device capable of storing, for example, multivalued data.
A NAND flash memory using an EEPROM has been proposed as an electrically rewritable nonvolatile semiconductor memory. In the NAND flash memory, the sources and drains of memory cells arranged side by side are connected in series and the series connection of the memory cells is connected as one unit to a bit line. In the NAND flash memory, all or half of the cells arranged in the direction of row are written into or read from all at once. Recently, a multivalued memory that enables data items to be stored in one cell in a NAND flash memory has been developed.
FIG. 3
shows the relationship between the data in a memory cell in an ordinary multivalued memory and the threshold voltage of the memory cell. The data items in a memory cell, or state “0” to state “3”, are defined in ascending order, starting from the lowest threshold voltage of the memory cell. When erasing is done, the data in the memory cell goes to state “0”. A write operation causes the threshold voltage of the cell to move to a higher level. When 2-bit data is stored in a single cell, the 2-bit data is separated into first-page data and second-page data. The first-page data and second-page data are switched using an address.
FIG. 4
shows a general method of writing data into a multivalued memory. When data is written into a memory cell, the first-page data is written. Then, the second-page data is written. When the write data constituting the first-page or second-page data is “1”, the threshold voltage of the memory cell does not change in the write operation, with the result that the data in the memory cell remains unchanged. Namely, the data is not written. When write data constituting the first-page or second-page data is “0”, the threshold voltage of the memory cell is changed in the write operation. As a result, the data in the memory cell is changed, causing the data to be written.
It is assumed that the data in the memory cell in the erased state is in state “0”. First, the first-page data is written into the memory cell. When the write data is “1”, the data in the memory cell remains in state “0”. When the write data is “0”, the data in the memory cell goes to state “1”.
Next, the second-page data is written. At this time, when write data “0” is externally supplied to the memory cell whose data has become state “1” as a result of the first-page write operation, the data in the memory cell is brought into state “3”. Moreover, when data “0” is externally supplied to the memory cell whose data has remained in state “0” as a result of the first-page write operation, the data in the memory cell is brought into state “2”.
Furthermore, when data “1” is externally supplied to the memory cell whose data has become state “1” as a result of the first-page write operation, the data in the memory cell is allowed to remain in state “1”. In addition, when data “1” is externally supplied to the memory cell whose data has remained in state “0” as a result of the first-page write operation, the data in the memory cell is allowed to remain in state “0”.
On the other hand, when the data stored in the memory cell is read, the second-page data is read first and the first-page data is read. With the definition of
FIG. 3
, when the second-page data is read, if the data in the memory cell is in state “0” or state “1”, the read-out data will be “1”. Furthermore, if the data in the memory cell is in state “2” or state “3”, the read-out data will be “0”. For this reason, when the second-page data is read, a judgment can be made through only one operation of judging whether the data in the memory cell is in either state “1” or blow or state “2” or above.
In contrast, when the first page data is read, if the data in the memory cell is in state “0” or state “2”, the data to be read will be “1”. If the data in the memory cell is in state “1” or state “3”, the data to be read will be “0”. Consequently, the first page requires a total of three read operations for the following judgments: a judgment whether the data in the memory cell is in either state “0” or state “1” or above, a judgment whether the data in the memory cell is in either state “1” or below or state “2” or above, and a judgment whether the data in the memory cell is in either state “2” or below or state “3”.
Therefore, an ordinary nonvolatile semiconductor memory device requires many operations in reading the data from the memory cells, taking a long time to read the data.
BRIEF SUMMARY OF THE INVENTION
It is, accordingly, an object of the present invention to overcome the above disadvantage by providing a nonvolatile semiconductor memory device capable of reducing the number of operations in reading data and shortening the data read time.
The foregoing object is accomplished by providing a nonvolatile semiconductor memory device comprising: a memory element which is connected to a bit line and a word line and stores one of state “0”, state “1”, state “2”, and state “3” of data that differ in threshold voltage; a data storage circuit which is connected to the bit line and stores not only data of a first or a second logical level externally supplied but also the data of the first or second level read from the memory element; and a control circuit which controls not only the potential on the bit line and that on the word line but also the operation of the data storage circuit, wherein the control circuit operates in such a manner that in a first operation, the control circuit changes the data in the memory element from the state “0” to state “1” when the data in the data storage circuit is data of the first logical level and keeps the data in the memory element in the state “0” when the data in the data storage circuit is data of the second logical level, that in a first verify operation of verifying whether the data has reached state “1”, the control circuit brings the data in the data storage-circuit to the second logical level when the data in the data storage circuit is at the first logical level and the data has reached state “1”, keeps the data in the data storage circuit at the first logical level when the data has not reached state “1”, keeps the data in the data storage circuit at the second logical level when the data in the data storage circuit is at the second logical level, and carries out the first operation until the data in the data storage circuit has reached the second logical level, and that in a second operation, the control circuit changes the data in the memory element from state “1” to state “2” when the data in the data storage circuit is data of the first logical level externally supplied and the data in the memory element is in state “1”, and changes the data in the memory element from state “0” to state “3” when the data in the memory element is in state “0”.
The foregoing object is further accomplished by providing a nonvolatile semiconductor memory device comprising: a memory element which is connected to a bit line and a word line and stores one of state “0”, state “1”, state “2”, and state “3” of data that differ in threshold voltage; a first storage circuit which is connected to the bit line and stores data of a first or a second logical level externally supplied; a second storage circuit which is connected to the bit line and stores the data of the first or second level read from the memory element; and a control circuit which controls not only the potential on the bit line and that on the word line but also the operation of the first and second storage circuits, wherein the control circuit operates in such a manner that in a first operation, the control circuit changes the data in the memory element from state “0” to state “1” when the data in the
Shibata Noboru
Tanaka Tomoharu
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