Nonvolatile semiconductor memory device equipped with means for

Details Nonvolatile semiconductor memory device equipped with means for Nonvolatile semiconductor memory device equipped with means for

1995-05-11

1996-08-13

Nelms, David C.

Static information storage and retrieval

Floating gate

Disturbance control

36518511, 36518513, 36518518, G11C 1134

Patent

active

055463398

ABSTRACT:
When a write operation is indicated, a control circuit which receives the power supply voltage, generates a write control signal C, two power source voltages V1 and V2 for write which are 2 V and 10 V, respectively. Upon receipt of the write control signal C a row decoder 103 brings the word line corresponding to the memory cell transistor to be written in to 10 V and the other wordlines to 2 V. Upon receipt of the write control signal C a source line control circuit 105 brings the source line corresponding to the memory cell transistor to be written in to 0 V and the other source lines to 5 V.

REFERENCES:
patent: 5267196 (1993-11-01), Talreja et al.
patent: 5384742 (1995-01-01), Miyakawa et al.
patent: 5428568 (1995-06-01), Kobayashi et al.

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