Nonvolatile semiconductor memory device carrying out...

Details Nonvolatile semiconductor memory device carrying out... Nonvolatile semiconductor memory device carrying out...

2007-07-02

2009-11-03

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185120, C365S185110, C365S185170, C365S185030, C365S185040, C365S185090

Reexamination Certificate

active

07613046

ABSTRACT:
A memory cell array has a first and a second storage area. The first storage area has a memory element selected by an address signal. The second storage area has a memory element selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

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JP Office Action dtd Aug. 21, 2007, JP Appln. 2000-297443.
CN Office Action dtd Jun. 1, 2007, CN Appln. 2004100421793.
JP Office Action Dec. 4, 2007, JP Appln. 2000-297443.
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