Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-05-08
2003-08-12
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185040, C365S185220, C365S185240
Reexamination Certificate
active
06606266
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the configuration of a nonvolatile semiconductor memory device and particularly relates to the configuration of a nonvolatile semiconductor memory device capable of storing multiple-bit information of two or more bits in one memory cell.
2. Description of the Background Art
In recent years, flash memories have been utilized as memory mediums for file storage (data storage) other than for program storage. To store data, it is necessary to increase storage capacity. As one of the techniques for realizing the mass storage capacity, there is proposed a so-called “multilevel data write” technique for writing data of two or more bits in one memory cell.
If two bits are stored in one memory cell, for example, it is required to store four values in each memory cell.
Conventionally, if writing such multilevel data, a write processing is carried out in such a sequence that a cell to which one of the four levels is to be written is selected, the level is written to the cell and then a cell to which the next level is to be written is selected and the next level is written to the cell.
In addition, to carry out an operation for determining whether or not desired data has been written, i.e., “a verification operation”, data which becomes an estimated value is generated for each level and the data is compared according to levels to thereby verify the data.
However, if four-level data is written so as to store two-bit information in one cell by the method described above, longer write time is disadvantageously required than the time to write two levels of one bit in one cell.
Furthermore, to further advance the mass storage of a flash memory to store data in the future, it will be necessary to store data of, for example, three bits in one cell, i.e., to store eight levels in one cell. In this case, far longer data write time is disadvantageously required.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a nonvolatile semiconductor memory device writing multilevel data in one cell and capable of shortening data write time.
In short, the present invention is a nonvolatile semiconductor memory device including: a memory cell array; a plurality of word lines; a row select circuit; a plurality of bit lines; a plurality of program data circuits; and a plurality of program sense circuits.
The memory cell array has a plurality of memory cells arranged in a matrix. Each of the memory cells includes storage elements capable of storing multilevel data in a nonvolatile manner. Each of the storage elements has a first node and a second node, and a level of a threshold value of each of the storage elements changed in the nonvolatile manner by applying a voltage at least between the first node and the second node is capable of having one of a plurality of levels corresponding to the multilevel data.
A plurality of word lines are provided to correspond to rows of the memory cell array, and are coupled to the first node of each of the storage elements belonging to the corresponding rows, respectively. The row select circuit is capable of selectively supplying a first pulse potential to each of the plurality of word lines in a write operation. A plurality of bit lines are provided to correspond to columns of the memory cell array, and are coupled to the second node of the plurality of the storage elements belonging to the corresponding columns, respectively.
A plurality of program data circuits are provided to correspond to the plurality of bit lines, and supply one of a second potential and a write prohibiting potential corresponding to the multilevel data to be written to the storage elements connected to the corresponding bit lines, to the corresponding bit lines in accordance with a write control signal in the write operation, respectively.
A plurality of program sense circuits are provided to correspond to the plurality of bit lines, compare threshold values of the storage elements sensed through the corresponding bit lines with reference potentials corresponding to the multilevel data to be written in a verification operation, and instruct the output of the write prohibiting potential by the write control signal if the threshold values become values corresponding to the multilevel data to be written, respectively.
Preferably, the row select circuit is capable of selectively supplying a predetermined read potential to each of the word lines in a read operation. Preferably, the nonvolatile semiconductor memory device further includes a plurality of read circuit groups provided to correspond to the plurality of bit lines. Each of the read circuit groups includes a plurality of read circuits. A plurality of read circuits receive a plurality of reference potentials for determining to which levels of the plurality of reference potentials corresponding to the multilevel data, levels of the threshold values of the storage elements correspond, and compare levels of the plurality of reference potentials with potential levels of the corresponding bit lines, respectively. Each of the reference potentials corresponds to a voltage dropped from the predetermined verification potential by one of the threshold voltages corresponding to the multilevel data. The nonvolatile semiconductor memory device further includes a data control circuit converting each of the potential levels of the bit lines into one of the multilevel data based on comparison results of the plurality of read circuits.
Therefore, one advantage of the present invention is that the data writing corresponding all the written data can be performed in parallel for a plurality of bit lines and a time for writing data can be shortened. That is, even if multilevel data is written to a memory cell, the write prohibiting voltage is sequentially applied to the bit lines for which data write has been finished. Further, since the reference potentials corresponding to the multilevel data to be written are compared with the threshold values of the storage elements in each of bit lines in the verification operation, it is also possible to perform the verification operation for a plurality of bit lines in parallel.
Another advantage of the present invention is that read rate can be accelerated in a multilevel data read operation.
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Atsushi Nozoe, et al, “A 256 Mb Multilevel Flash Memory with 2MB/'s Program Rate for Mass Storage Applications” MP 6.5, 1999 IEEE International Solid-State Circuits Conference.
Auduong Gene N.
Ho Hoai
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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