Nonvolatile semiconductor memory device capable of uniformly...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S185240, C365S185030, C365S205000, C365S189011

Reexamination Certificate

active

06856550

ABSTRACT:
At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.

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“Can NROM, a 2 bit, Trapping Storage NYM Cell, Give a Real Challenge to Floating Gate Cells?”, Boaz Eitan et al., the 1999 International Conference on Solid State Devices and Materials, Tokyo, Sep. 1999, pp. 522-524.
Related U.S. Appl. No. 10/146,021 filed May 16, 2002 (Our Reference No. 57454-581).
Related U.S. Appl. No. 10/146,031 filed May 16, 2002 (Our Reference No. 57454-562).
Related U.S. Appl. No. 10/211,338 filed Aug. 5, 2002 (Our Reference No. 57454-703.)

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