Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-12-17
2000-05-23
Nguyen, Viet Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518523, 36518508, G11C 1606
Patent
active
060672536
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an improvement in nonvolatile semiconductor memory device (EEPROM) which can electrically rewrite/erase information.
BACKGROUND ART
(Description of Prior Art)
Nonvolatile semiconductor memory devices can be roughly classified, on the basis of their stored information rewrite operations, into (1) a scheme for write access by hot electrons/erasure by a tunnel current and (2) a scheme for write access by a tunnel current/erasure by a tunnel current.
A flash EEPROM is a typical nonvolatile semiconductor memory device which employs the former scheme (1). In the flash EEPROM, a write voltage (high voltage Vpp) is applied to both the control gate and the drain electrode of a MOS transistor which constitutes a memory cell to inject hot electrons into the floating gate, thereby performing a write operation.
In such an EEPROM, the threshold value of the memory cell transistor changes depending on the channel length of the memory cell MOS transistor, the thickness (tunnel oxide film thickness) of an insulating film through which a tunnel current flows under the floating gate, a change in electrode voltage between the source and drain, or the like. As a result, the distribution (data "0") of threshold voltage VTH after information is written in each memory cell transistor largely varies, as shown in the upper-side hatched graph of FIG. 7A or 7B.
On the other hand, in an erase operation, the control gate of the memory cell MOS transistor is grounded. An erase voltage (Vpp) is applied to the source electrode (or the drain electrode) to extract electrons captured by the floating gate to the source electrode (or the drain electrode) side in the form of a tunnel current. In this erase operation as well, the distribution (data "1") of threshold voltage VTH of the memory cell transistor after the erase operation largely varies, as shown in the lower-side hatched graph of FIG. 7A or 7B, depending on a variation in the control gate voltage (word line voltage), the drain voltage (bit line voltage), the film thickness of the tunnel oxide film, or the like, as in the write operation.
An NAND type EEPROM is a typical nonvolatile semiconductor memory device which employs the latter scheme (2). In this NAND type EEPROM, the write and erase operations are performed by a tunnel current from the floating gate of a MOS transistor which constitutes a memory cell.
The tunnel current of the scheme (2) varies depending on a variation in the word line voltage (control gate voltage), the bit line voltage (drain voltage), the film thickness of the tunnel oxide film, or the like, as in the above-described erase operation of the scheme (1). For this reason, in the scheme (2) as well, the distributions of threshold voltage VTH of the memory cell transistor in the write and erase operations largely vary, as shown in the upper- and lower-side hatched graphs of FIG. 7C.
In the example shown in FIG. 7B, of the variations in threshold voltage VTH, the high-voltage side variations (data "0" write operation) are distributed on the upper side of the read operation voltage (+5 V of TTL level) of the EEPROM, so no serious problem is posed. However, the low-voltage side variations (data "1" erase operation) in threshold voltage VTH are distributed in the range of the read operation voltage (+5 V of TTL level) of the EEPROM and largely affect the data read operation.
A device in which the variation in threshold value is suppressed is disclosed in Japanese Patent Application No. 6-222734 (corresponding to U.S. Ser. No. 08/516,830 filed on Aug. 18, 1995) filed by the present applicant on Aug. 25, 1994. According to the this prior invention, variations in threshold values of a large number of memory cell transistors can be suppressed and minimized.
In this prior invention, however, after electrons are extracted from the floating gate of the memory cell transistor, the bit line potential varies. This potential variation may adversely affect the subsequent circuit operation (e.g., decrease the set potent
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Nguyen Viet Q.
NKK Corporation
Tran Andrew Q.
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