Nonvolatile semiconductor memory device capable of storing analo

Details Nonvolatile semiconductor memory device capable of storing analo Nonvolatile semiconductor memory device capable of storing analo

1998-02-09

1999-10-26

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518503, 257316, G11C 1400

Patent

active

059739606

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and in particular, relates to a memory device which is capable of storing analog or many-valued data at high speed and with a high degree of accuracy.
2. Description of the Related Art
In recent years, in concert with the development in computer technology, the progress in the field of data processing technology has been truly remarkable. However, when attempts were made to realize the flexible type of data processing conducted by human beings, it was almost impossible to obtain the results of such calculations in real time using present computers. The reasons advanced for this are that the data which human beings process in the course of their daily lives are analog data, so that there is firstly an enormous amount of such data, and moreover, these data are inexact and vague. It is thus a problem in present data processing systems that the extremely redundant analog data are all converted into digital values, and rigorous digital operations are conducted one by one.
An example of this is image data. For example, if one screen is incorporated into a 500.times.500 two dimensional array, then the total number of pixels is 250,000, and when the strength of the three colors red, green, and blue for each pixel is expressed in terms of eight bits, then the amount of data in one stationary image reaches 750,000 bits. In moving images, the amount of image data increases with time. Even if a present day supercomputer is used, it is impossible to manipulate the large amount of (1)/(0) data and conduct picture recognition and understanding in real time.
On the other hand, attempts have been made to realize data processing approximating that of human beings by accepting real world data, which are analog values, in an unchanged form and conducting calculations and processing on these analog values, in order to overcome the problems described above. As a result, a number of memory devices have been invented.
As one of these devices, the present inventors have proposed, in Japanese Patent Application No. Hei 7-2944, a memory device which is capable of writing desired analog values using simple circuitry such as that shown in FIG. 9 (title of the invention: Nonvolatile semiconductor Memory, date of application: Jan. 11, 1995). First an explanation of the cell of this technology will be made.
Reference 901 indicates an NMOS transistor, while reference 902 indicates a floating gate formed from, for example, N.sup.+ polysilicon; this controls the ON and OFF state of NMOS 901. NMOS drain 903 is connected to power source line 904, while source 905 is connected to an external capacity load 906; the structure is such that the circuit operates as a source follower circuit and reads out a potential V.sub.FG of the floating gate 902 to the exterior as V.sub.OUT. Reference 907 indicates an electrode which is capacitively coupled with floating gate 902; in this example, it is grounded. The capacitive coupling coefficient thereof is represented by C.sub.1. Reference 908 indicates a charge transfer electrode; it is connected with the floating gate via a tunnel junction 909 which is an oxide film of approximately 10 nm. The capacitance of this tunnel junction 909 is represented by C.sub.2. Charge transfer electrode 908 is connected to writing high voltage application electrode 911 via a capacitance 910 (the size thereof is represented by C.sub.3). Reference 912 indicates an NMOS transistor; the ON and OFF state thereof is controlled by the output line 913 of the inverter. NMOS transistor 914 serves to connect the input 915 of a control circuit constructed using an inverter to a memory cell. The input 915 of the control circuit is capacitively coupled with input of inverter 916, and the input of inverter 916 and output 917 are connected via NMOS transistor 918. Output 917 controls the ON and OFF state of NMOS transistor 912 via a further stage inverter.
The readout principle is simple; NMOS 914 is placed in a

REFERENCES:
patent: 5065366 (1991-11-01), Bennett et al.
patent: 5450354 (1995-09-01), Sawada et al.
patent: 5559736 (1996-09-01), Matsukawa et al.

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