Nonvolatile semiconductor memory device capable of reducing...

Details Nonvolatile semiconductor memory device capable of reducing... Nonvolatile semiconductor memory device capable of reducing...

2000-07-10

2001-06-05

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290, C365S185270

Reexamination Certificate

active

06243292

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device capable of electrically writing and erasing data and retaining its data when power is removed.
2. Description of the Background Art
Nonvolatile semiconductor devices are mounted in systems as memory devices capable of retaining data in a nonvolatile manner at portable terminals to comply with the recent development in digital communication networks using portable information terminals such as portable telephones, internets and the like. Among such nonvolatile semiconductor memory devices, for example, there is a flash memory which is capable of collectively and electrically erasing stored data by a prescribed number of bits and electrically writing data.
FIG. 16
is a schematic diagram showing a cross sectional structure of a memory cell transistor of a so-called NOR flash memory, among such flash memories, in conjunction with the first erasing operation.
Referring to
FIG. 16
, a memory cell of the flash memory is provided with a multilayer gate disposed on a P well
10
formed in a main surface of the semiconductor substrate. The multilayer gate is provided with a gate oxide film
13
, a floating gate
14
of polycrystalline silicon or the like, an insulating film
15
generally called an ONO film having three layers of an oxide film, nitride film, and oxide film for preventing leakage, and a control gate
16
formed of polycrystalline silicon or the like. In vicinity of the multilayer gate on P well
10
, an N type source region
12
a
and drain region
12
b
are formed in a self-aligning manner.
In the following description, assume that a source voltage Vs, a drain voltage Vd, a control voltage Vcg, and a well potential Vw are respectively applied to the source region, drain region, control gate and P well
10
.
In the erasing operation of the memory cell of the flash memory shown in
FIG. 16
, a high voltage Vpp (up to 10V) obtained by boosting an external power supply voltage is applied as source voltage Vs to a source of the memory cell. The drain is brought into a floating state. A ground potential is used as potential Vw of P well
10
. Thus, electrons accumulated in floating gate
14
can be extracted and swept into the side of the source.
FIG. 17
is a diagram showing a cross sectional structure of a memory cell array in which such NOR type flash memories are arranged.
In the structure shown in
FIG. 17
, bit lines are hierarchically divided into a main bit line MBL and sub bit lines SBL
1
and SBL
2
respectively connected to main bit line MBL via select transistors Trs
1
and Trs
2
, in order to make a data writing unit as small as possible. More specifically, data is only written to the memory cell block connected to sub bit line SBL
1
(or SBL
2
) selected by select transistor Trs.
As in
FIG. 16
, if the erasing operation is performed by extracting electrons from the source, a back gate of the memory cell transistor, or P well
10
, can be shared by blocks to be erased and select transistors.
On the other hand, in an erasing method of an NOR type flash memory, a high voltage is applied to the back gate of the memory cell, or P well
10
, so that electrons in floating gate
14
is extracted and swept into the side of P well
10
and a threshold voltage Vth of the memory cell transistor is decreased.
FIG. 18
is a schematic diagram shown in conjunction with a second erasing method of such an NOR type flash memory.
As shown in
FIG. 18
, in the second erasing method, source potential Vs and drain potential Vd of the memory cell transistor are both equal to a boosted potential Vpp, and a potential of the P well is also equal to boosted potential Vpp.
A potential of the control gate is for example equal to a ground potential.
FIG. 19
is a cross sectional view shown in conjunction with a structure of a memory cell array when data is erased by extracting electrons from such a P well
10
(a back gate).
In the method shown in conjunction with
FIG. 18
, as the erasing operation is performed by extracting electrons toward the side of P well
10
, P wells
10
.
1
and
10
.
2
must be separated by an N well
8
for every data writing unit (a memory block). In addition, also for select transistors Trs
1
and Trs
2
which select memory blocks for a writing operation, a P well
10
.
0
including select transistors Trs
1
and Trs
2
must be separated from P wells
10
.
1
and
10
.
2
of the writing units, i.e., memory blocks.
As described above, although the second erasing method has an advantage over the first erasing method in terms of reliability and the like, the wells for the memory blocks as writing units and the well for select gates Trs
1
and Tr
2
must be separated. Thus, a region required for separation of wells increases, whereby a memory cell area as a whole disadvantageously increases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of preventing an increase in area of a memory cell array while maintaining reliability of the memory cell transistor.
In short, the present invention is a nonvolatile semiconductor memory device formed in a main surface of a semiconductor substrate including an internal power supply circuit, a memory cell array, a plurality of first well regions of a first conductivity type, a second well region of a second conductivity type, a plurality of main bit lines, a plurality of sub bit lines, a plurality of select transistors, and a cell select circuit.
The internal power supply circuit receives an external power supply potential for generating an internal potential.
The memory cell array includes a plurality of memory cell transistors arranged in a matrix each capable of storing data in a nonvolatile manner and electrically writing and reading data. The memory cell array is divided into a plurality of memory cell blocks each serving as a unit collectively subjected to an erasing operation.
The plurality of first well regions of the first conductivity type are provided in the main surface of the semiconductor substrate corresponding to memory cell blocks, and provided with memory cell transistors belonging to respective memory cell blocks. The second well region of the second conductivity type electrically separates the plurality of first well regions.
The plurality of main bit lines are shared by the plurality of memory cell blocks corresponding to columns of the memory cell array. The plurality of sub bit lines are provided corresponding to columns of memory cell transistors for every memory cell block and connected to respective memory cell transistors.
The plurality of select transistors are provided corresponding to sub bit lines and each selectively connecting corresponding sub bit line and corresponding one of the plurality of main bit lines. The cell select circuit applies a potential related to a conductive state to a gate of a selected select transistor and applies a potential related to a cut-off state to a gate of a non-selected select transistor of a plurality of select transistors.
Each of the select transistors is provided in one of the plurality of first well regions that also includes the memory cell transistor to which the corresponding sub bit line is connected.
Therefore, a main advantage of the present invention is that a considerable reduction in area of the memory cell array as well as in chip size can be achieved as the memory cell transistor and the select transistor are formed in the same well.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5392238 (1995-02-01), Kirisawa
patent: 5994732 (1999-11-01), Ajika et al.
patent: 6038170 (2000-03-01), Shiba
patent: 9-307005 (1997-11-01), None
patent: 11-3595 (1999-01-01), None

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