Nonvolatile semiconductor memory device capable of high...

Details Nonvolatile semiconductor memory device capable of high... Nonvolatile semiconductor memory device capable of high...

2000-12-14

2002-05-07

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S189090, C365S226000

Reexamination Certificate

active

06385086

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and particularly, to a nonvolatile semiconductor memory device including an amplifier circuit outputting power supply potentials at a plurality of levels covering from a voltage higher than an external power supply potential to the ground potential.
2. Description of the Background Art
In recent years, nonvolatile semiconductor memory devices have been adopted for data storage in company with proliferation of portable information equipments in industrial and consumer uses. One of nonvolatile semiconductor devices is a flash memory.
In a memory cell of a flash memory, information of “0” or “1” is stored by injection into or extraction from a floating gate holding electrons. When such injection or extraction of electrons is effected, there arises a need to apply high voltages at a plurality of levels on a memory cell.
Below, description will be given of a case where a plurality of different potentials are applied on a memory cell of a NOR memory as an example.
FIG. 34
is a conceptual diagram for describing a programming operation on a memory cell.
Referring to
FIG. 34
, a word line WL
0
is set to about 8 V and word lines WL
1
to WL
3
are set to 0 V. A sub-bit line SBL
1
is set to 4 V and a sub-bit line SBL
0
is set to 0 V. Further, a well in which a memory block to be programmed is formed is set to 0 V and a Source line SL is set to 0 V.
With such settings, a memory transistor connected to the word line WL
0
and the sub-bit line SBL
1
is selected. Electrons are injected into the floating gate of the selected memory transistor to hold a data “0” therein.
FIG. 35
is a schematic sectional view for describing a programming operation on the selected cell of FIG.
34
.
Referring to
FIG. 35
, about 8 V of a high positive voltage is applied on the word line WL and about 4 V of a positive voltage is applied on the sub-bit line SBL. In this state, potentials of a P well and the source line SL are set to 0V and thereby, electrons are injected from the P well and the source S into the floating gate F. By injecting the electrons, a threshold voltage Vth of the selected memory transistor changes up to about 6 V or higher; which operation is a programming operation.
It should be appreciated that, for convenience in description, an impurity region connected to the source line SL is referred to as a source S and further, an impurity region facing the source S with a channel region interposed therebetween is referred to as a drain D.
FIG. 36
is a conceptual circuit diagram for describing an erase operation on a memory cell.
Referring to
FIG. 36
, when an erase operation is performed, the word lines WL
0
to WL
3
in a block to be erased are collectively set to about −10V. On the other hand, a potential of a well in which the memory block to be erased is formed is set to about 8 V and the source line SL is also set to about 8 V. Further, the sub-bit line SBL connected to the memory block to be erased is set to the open state by setting a selected gate to the non-conductive state.
In such settings, memory transistors residing in the same well are collectively applied with a high electric field. Electrons are extracted from the floating gates of the memory transistors in the memory blocks to be erased, and an erase operation is effected that a threshold voltage Vth of each memory transistor is collectively reduced down to a voltage of the order ranging from 1 V to 3 V from the high state.
FIG. 37
is a schematic sectional view for describing a potential set on each memory transistor in an erase operation.
Referring to
FIG. 37
, the gate G of the memory transistor is set to about −10 V through the word line WL. The source S is set to about 8 V through the source line SL. The drain D is in the open state since the sub-bit line SBL is disconnected from a main bit line MBL. Further, the P well is set to about 8 V.
With such potential settings, electrons are extracted from the floating gate F into the P well and the source S and a threshold voltage Vth of the memory transistor, which has been 6 V or higher, Changes to a value ranging from 1 to 3 V, that is the memory transistor is put into the erased state.
A high voltage applied on a memory cell is generally generated by a charge pump circuit incorporated within a semiconductor memory device.
FIG. 38
is a block diagram for describing a conventional configuration whereby a plurality of high voltages are generated.
Referring to
FIG. 38
, a charge pump circuit
952
outputs an output potential Vout obtained by receiving and boosting a power supply potential Vcc supplied externally and the ground potential. The output potential Vout is monitored by a potential detection circuit
954
. The potential detection circuit
954
compares a potential specified by a control signal SET supplied from a control portion of the semiconductor memory device and the output potential of the charge pump circuit
952
with each other. When the output potential Vout is lower than the specified potential, the potential detection circuit
954
drives the charge pump circuit
952
. On the other hand, when the output potential Vout rises to be higher than the specified potential, the potential detection circuit
954
ceases the operation of the charge pump circuit
952
.
When high voltages at a plural levels are necessary, it is not justified from the view point of integration to incorporate charge pump circuits for the respective voltages into the memory device. Further, when a configuration and operation are adopted in which control signals SET provided from a control portion are switched over to switch potentials detected by the voltage detection circuit
954
over and attain a plurality of high potentials, using a single charge pump circuit, it takes a long time to stabilize an output potential Vout.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a nonvolatile semiconductor memory device including a voltage amplifier circuit that can receive an output of a single charge pump circuit or outputs of charge pump circuits whose number is smaller than a necessary number of potential levels as a power supply potential or power supply potentials to generate a plurality of output potentials.
Briefly stated, the present invention provides a nonvolatile semiconductor memory device including: a memory array; a control portion and a voltage generation portion.
The memory array includes a plurality of memory cells, arranged in a matrix pattern, and each holding a data in a nonvolatile fashion. The control portion performs control of voltage application on a plurality of memory cells according to an instruction supplied externally. The voltage generation portion outputs a first internal potential applied on the plurality of memory cells in erasure and rewriting of the data from an output node thereof according to an output of the control portion.
The voltage generation portion includes: a booster circuit raising a first power supply potential to output a second power supply potential; a standard potential generation portion generating a second internal potential according to an instruction of the control portion; and a voltage amplifier circuit receiving the second power supply potential and transmitting the first internal potential to the output node according to the second internal potential.
The voltage amplifier circuit includes: a standard potential input portion receiving the second internal potential to output a third internal potential; and a drive portion driving a potential at the output node according to the third internal potential.
The standard potential input portion includes: a first field effect transistor whose source is coupled to the second internal potential, and whose drain and gate are coupled to the third internal potential; and a first current source, provided between a first internal node applied with a prescribed power supply potential and the first field transistor, and supplying a pr

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