Nonvolatile semiconductor memory device capable of erasing...

Details Nonvolatile semiconductor memory device capable of erasing... Nonvolatile semiconductor memory device capable of erasing...

2000-11-13

2002-01-01

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185020, C365S185180, C365S185240, C365S185300

Reexamination Certificate

active

06335882

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device capable of writing/erasing electrical data and storing information even when a power supply source is turned off.
2. Description of the Background Art
A nonvolatile semiconductor memory device, e.g., a flash memory, has a memory cell array with memory cell transistors having floating gates arranged. The flash memory can electrically write/erase data of the memory cells. Recently, such flash memories are widely used for a data storage application of temporarily storing data in a nonvolatile manner in a system such as a digital still camera, digital audio, and flash card.
In the flash memory, a writing/erasing operation is performed by applying a high voltage to a floating gate which is insulated by an insulation film from a periphery portion in the memory cell transistor to charge or discharge electrons so that the threshold voltage of the memory cell transistor is changed. In the flash memory used for the data storage application, unlike in the conventional application of retaining a program for operating a system, for example, a data unit (the number of memory cells that are collectively processed) not only to be written but also to be erased is desirably small because the writing operation per se must be frequently performed.
FIG. 22
is a schematic block diagram showing an arrangement of a memory cell array of an AND flash memory.
A memory cell MC
001
is a floating gate type transistor having a gate, drain and source. Memory cell MC
001
has its gate connected to a word line WL(
0
), its drain connected to a global bit line GBL
1
through a sub bit line SBL and a select transistor STR
1
, and its source connected to a source line SL through a select transistor STR
2
. 128 memory cells are connected to sub bit line SBL, and 128 word lines form one physical unit. This is referred to as “a physical block.”
The writing/erasing operation with respect to the memory cells is usually performed on every word line (hereinafter referred to as “one sector”). The writing operation is performed by applying a positive high voltage (of for example 18 V) to a word line to increase the threshold value of the memory cell.
It is noted that a positive writing preventing voltage (of for example 6 V) is applied to the memory cells to which data is not to be written so as to prevent increase in the threshold value.
The erasing operation is performed by applying a negative high voltage (of for example −17 V) to the word line to decrease the threshold value of the floating gate transistor forming the memory cells.
The writing/erasing operation is automatically performed by a control circuit in the flash memory. In the automatic erasing operation, an operation of determining as to if the memory cell has attained to a threshold value in a desired range (hereinafter referred to as “a verify operation”), such as an operation of applying an erasing pulse to a target sector, is repeated. Then, the operation is stopped when the threshold values of all memory cells fall in the desired range, and the completion of the erasing operation is notified to an external system.
When the system requests writing of a data unit greater than one sector, the writing time can be reduced by performing the automatic erasing operation simultaneously on a plurality of sectors. The automatic erasing for every sector is referred to as “sector erasing,” whereas the automatic erasing performed simultaneously on the plurality of sectors is referred to as “block erasing.”
FIG. 23
is a graph showing a relationship between a threshold value distribution of the memory cell transistors in a block (a plurality of sectors) to be erased and a verify voltage.
FIG. 24
is a flow chart showing an exemplary operation of the block erasing (when one block includes 8 sectors).
Referring to
FIGS. 23 and 24
, when the block erasing operation is started (a step S
1000
), a sector address is reset such that AX=0 (a step S
1002
).
Thereafter, erasing pulses are applied collectively to eight sectors (a step S
1004
) and, successively, a determination is made as to if the threshold voltages of the memory cells in the first sector have become for example equal to or smaller than 1.6 V (hereinafter indicated as VF
1
) (this operation is hereinafter referred to as “erasing verify”) (a step S
1006
).
If it is determined that the threshold voltage has not become equal to or smaller than a potential VF
1
as a result of the erasing verify, a process returns to step S
1004
. Such pulse application and erasing verify are repeated. If it is determined that the threshold voltages of all memory cells in the first sector have become equal to or smaller than potential VF
1
(1.6 V) (a step S
1006
), a determination is made as to if an erasing operation on eight sectors has been completed (a step S
1008
).
If it is determined that the process on eight sectors has not yet been completed, the sector address is incremented (a step S
1010
), and step S
1006
is performed on the second sector, so that a verify operation is performed as in the case of the first sector.
If it is determined that the erasing verify has been performed on all of the eight sectors in a step S
1008
, the sector address is reset again (a step S
1012
).
Thereafter, an operation of checking as to if there is any memory cell of which threshold voltage has become too low (hereinafter referred to as “over-erasing verify”) (a step S
1014
).
If it is determined that the threshold voltage has become too low as a result of the over-erasing verify operation (step S
1014
), a writing operation is selectively performed on the memory cell that has failed the over-erasing verify, i.e., the memory cell of which threshold voltage has become equal to or smaller than 0.9 V (hereinafter indicated as VF
2
) (a step S
1012
).
A determination is made as to if the threshold voltage has increased at least to potential VF
2
by the above mentioned selectively performed writing operation (a step S
1022
) and, if the threshold value has not increased at least to potential VF
2
, the selectively performed writing process performed again (step S
1020
). On the other hand, if it is determined that the threshold voltage has become at least potential VF
2
(step S
1022
), it is again verified as to if there is any cell of which threshold value has become at least 1.9 V (hereinafter indicated as VF
3
) (this operation is hereinafter referred to as “over-writing verify”) (step S
1024
).
If it is determined that the threshold value is at least potential VF
2
and at most potential VF
3
as a result of the over-writing verify, the process proceeds to a step S
1016
.
Meanwhile, the process also proceeds to step S
1016
even if it is determined that the threshold voltage is not at most potential VF
2
as a result of the over-erasing verify in step S
1014
.
A determination is made as to if the over-erasing verify has been performed on eight sectors in step S
1016
and, if the process on the eight sectors has not yet been completed, the sector address is incremented (step S
1018
) and the process returns to the step of the over-erasing verify (step S
1014
).
If it is determined that the process on the eight sectors has been completed (step S
1016
), the erasing operation normally ends (a step S
1030
).
In the step S
1024
, if the overwriting verify reveals that the threshold value exceeds the potential VF
3
as a result of the overwriting caused by the writing verify so performed that the threshold values are rendered above the potential VF
2
, the erasing operation abnormally ends (step S
1026
)
In the erasing verify operation, as shown in
FIG. 22
, the voltage of the selected word line of the sector to be subjected to the erasing verify is set such that VF
1
=1.6 V, whereas the voltage of the non-selected word lines of other sectors is set such that VF
0
=−2 V.
The global bit line is precharged to about 1 V. When select transistors STR
1
and STR
2
are t

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