Nonvolatile semiconductor memory device capable of correctly...

Details Nonvolatile semiconductor memory device capable of correctly... Nonvolatile semiconductor memory device capable of correctly...

2000-11-22

2002-07-09

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S205000, C365S185200

Reexamination Certificate

active

06418057

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a nonvolatile semiconductor memory device in which memory cell information is latched in latch circuits and accesses are sequentially made thereto.
2. Description of the Background Art
A nonvolatile memory cell storing information in a nonvolatile manner has a stacked gate structure with a floating gate and a control gate, wherein a threshold voltage is changed according to an amount of changes accumulated in the floating gate and digital information of “1” or “0” is stored thereon according to a high level or a low level of the absolute value of the threshold value. Since the stored information is determined by an electric charge amount in the floating gate, and the floating gate is in an electrically floating state, information can be stored even after the power is switched off.
FIG. 14
is a circuit diagram showing a configuration of an array section of a conventional nonvolatile semiconductor memory device. In
FIG. 14
, this nonvolatile semiconductor device includes two memory arrays MAR and MAL. In the memory array MAR, memory cells MC are disposed in a matrix of rows and columns and also in the memory array MAL, memory cells MC are disposed in a matrix of rows and columns. In the memory array MAR, bit lines BLR are disposed corresponding to respective columns of memory cells MC, while word lines WLR are disposed corresponding to respective rows of memory cells MC. In
FIG. 14
, there are represented memory cells MC disposed in one row and four columns or bit lines BLR
1
to BLR
4
corresponding to respective columns and the word line WLR corresponding to the row.
In the memory array MAL, likewise, bit lines BLL (BLL
1
to BLL
4
) are disposed corresponding to respective columns of memory cells MC, while word lines WLL are disposed corresponding to respective rows of memory cells MC. The bit lines BLR and BLL are disposed in a mutually corresponding manner in memory arrays MAL and MAR. Each bit line BLR is provided with a precharge transistor PR (PR
1
to PR
4
) precharging an associated bit line BLR to a prescribed voltage level in response to a precharge instructing signal C
1
or C
2
, while each bit line BLL is provided with a precharge transistor precharging an associated bit line BLL to a prescribed voltage level in response to a precharge instruction signal D
1
or D
2
.
Between the memory arrays MAR and MAL, latch circuits LTH (LTH
1
to LTH
4
) are disposed corresponding to respective pairs of bit lines BLR and BLL. Each of the latch circuits LTH
1
and LTH
4
includes a pair of cross-coupled P channel MOS (Insulated Gate Field Effect) transistors Q
1
and Q
2
; and a pair of cross-connected N channel MOS transistors Q
3
and Q
4
. The latch circuit LTH (LTH
1
to LTH
4
) performs differential amplification of a signal on a latch node LNR (LNR
1
to LNR
4
) and a signal on a latch node LNL (LNL
1
to LNL
4
), and latch resultant complementary signals. Power supply nodes SP
1
and SN
1
of each of the odd-numbered latch circuits LTH
1
and LTH
3
are coupled to receive sense drive signals P
1
and N
1
, while power supply nodes SP
2
and SN
2
of each of the even-numbered latch circuits LTH
2
and LTH
4
are coupled to receive sense drive signals P
2
and N
2
.
Between bit lines BLR
1
to BLR
4
and corresponding latch circuits LTH
1
to LTH
4
, there are disposed transfer gates XR
1
to XR
4
for connecting the bit lines to the corresponding latch circuits when made conductive. The odd-numbered transfer gates XR
1
and XR
3
becomes conductive in response to a transfer instructing signal T
1
, while the even-numbered transfer gates XR
2
and XR
4
becomes conductive in response to a transfer instructing signal T
2
.
Further, between bit lines BLL
1
to BLL
4
and corresponding latch nodes LNL
1
to LNL
4
of the latch circuits LTH
1
to LTH
4
, there are disposed respective transfer gates XL
1
to XL
4
. The odd-numbered transfer gates XL
1
and XL
3
becomes conductive in response to the transfer instructing signal T
1
, while the even-numbered transfer gates XL
2
and XL
4
becomes conductive in response to the transfer instructing signal T
2
.
In order to perform programming/erasure verification, there are provided determination transistors DTR
1
to DTR
4
that become conductive in response to signal potentials on the latch nodes LNR
1
to LNR
4
and drives a coincidence detection line
2
r
to the ground voltage level when conductive and further, there are provided determination transistors DTL
1
to DTL
4
that become conductive in response to signal potentials on the latch nodes LNL
1
to LNL
4
and drives a coincidence detection line
2
l
to the ground voltage level when being conductive. The coincidence detection lines
2
r
and
2
l
are provided with respective current detecting circuits
3
r
and
3
l
. The current detecting circuits
3
r
and
3
l
detect whether or not current flows on the respective coincidence detection lines
2
r
and
2
l
, and according to detection results, detect whether or not corresponding latch nodes LNRs and LNLs are at the same logic level. Now, description will be made of operations in data read of the nonvolatile semiconductor memory device represented in
FIG. 14
with reference to a signal waveform diagram represented in FIG.
15
.
It should be noted that in
FIG. 15
, there are presented signal waveforms of the bit lines BLR
1
, BLL
1
, BLR
2
and BLL
2
when a power supply voltage is 3 V and a word line WLL is selected.
In the standby state, the bit lines BLR (indicating the bit lines BLR
1
to BLR
4
representatively hereinafter) and BLL (indicating the bit lines BLL
1
to BLL
4
representatively hereinafter) are at the ground voltage level and further, the word lines WLR and WLL are also at the ground voltage level.
In a programming operation, the precharge instructing signal C
1
, first, is set to 1V+Vth (pr). Here, Vth (pr) indicates a threshold voltage of the precharge transistor PR (PR
1
to PR
4
). Likewise, the precharge instructing signal D
1
is set to 0.5V+Vth (pl). Here, Vth (pl) indicates a threshold voltage of the precharge transistors PL
1
to PL
4
. In a case where 3 V is transmitted to the power supply nodes
1
r
and
1
l
, the precharge transistors PR
1
and PR
3
precharge the bit lines BLR
1
and BLR
3
to a voltage level of 1 V. On the other hand, the precharge transistors PL
1
and PL
3
precharge the bit lines BLL
1
and BLL
3
to a voltage level of 0.5 V.
In parallel to the precharge operation, sense drive signals P
1
and N
1
are both set to a voltage level of 0.5 V. When the sense drive signals P
1
and N
1
go to 0.5 V, the latch nodes LNR
1
, LNL
1
, LNR
3
and LN
3
are precharged to a voltage level of 0.5 V since the power supply nodes SP
1
and SN
1
in the latch circuits LTH
1
and LTH
3
both go to 0.5 V. After the precharge operation is completed, the word line WLR is driven into the selected state of a voltage of 3 V while keeping the bit lines BLR and BLL in an electrically floating state.
In the bit line BLR
1
, memory cell MC is put into the on state or the off state according to stored information thereof. When a threshold voltage of the memory cell MC connected to the bit line BLR
1
is high, the memory cell MC maintains the off state and the bit line BLR
1
maintains the precharge state even if the word line WLR is driven to 3 V. On the other hand, when a threshold voltage of the memory cell MC connected to the bit line BLR
1
is low, the memory cell MC connected to the bit line BLR
1
is put into the on state, a current flows from the bit line BLR
1
to a source node (ground node) through the memory cell MC and a voltage level of the bit line BLR
1
decreases to the ground voltage level. Contrast to the bit line BLR
1
, in the bit line BLR
2
, no precharge operation is performed, the word line WLL stays in the non-selected state and the bit line BLR
2
maintains the ground voltage level.
Word line WLR is driven into the no

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