Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2004-01-05
2004-11-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S185330
Reexamination Certificate
active
06826085
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to the adjustment of a step-up voltage thereof.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as a flash electrically erasable and programmable read only memory (EEPROM) device, a step-up voltage higher than an external power supply voltage is required for a write operation and an erase operation. Usually, such a step-up voltage is internally generated by using a step-up circuit.
The lower the step-up voltage, the larger the number of defective write/erase operations. On the other hand, the higher the step-up voltage, the shorter the life time of the device. Therefore, it is important to adjust the step-up voltage to a desired value. Note that this desire value is preferably a little higher than the minimum voltage by which a write or erase operation can be carried out.
In a prior art nonvolatile semiconductor device, in order to decrease a writing operation time and improve the reliability, the step-up voltage is gradually changed during a write operation (see: JP-A-2000-113690).
In the above-described prior art nonvolatile semiconductor memory device, however, since it is not easy to adjust the step-up voltage accurately and quickly, the device would be deemed to be defective and scrapped in spite of the fact that the device can be normally operated, which would decrease the manufacturing yield.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of accurately and quickly adjusting a step-up voltage.
According to the present invention, in a nonvolatile semiconductor memory device including a nonvolatile cell circuit, a step-up circuit receives a clock signal to generate a step-up voltage for the nonvolatile cell circuit. A voltage divider divides the step-up voltage to generate a plurality of voltages. A selector selects one of the voltages. A reference voltage generating circuit generates a reference voltage. A first comparator compares the selected one of the voltages with the reference voltage. A gate circuit supplies the clock signal to the step-up circuit in accordance with an output signal of the first comparator so that the selected one of the voltages is brought close to the reference voltage. Also, a second comparator compares the step up voltage with an externally-provided expected value. A counting signal generating circuit generates a counting signal in accordance with an output signal of the first comparator. A counter changes a value thereof by receiving the counting signal. Thus, the selector selects the one of the voltages in accordance with the value of the counter, so that the step-up voltage is brought close to the expected value.
REFERENCES:
patent: 5553021 (1996-09-01), Kubono et al.
patent: 6038173 (2000-03-01), Yero
patent: 6351417 (2002-02-01), Shiga et al.
patent: 6563737 (2003-05-01), Khouri et al.
patent: 2000-113690 (2000-04-01), None
NEC Electronics Corporation
Phan Trong
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