Nonvolatile semiconductor memory device capable of...

Details Nonvolatile semiconductor memory device capable of... Nonvolatile semiconductor memory device capable of...

2002-01-28

2002-10-15

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185300

Reexamination Certificate

active

06466484

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having floating-gate storage elements and a driving method therefor.
2. Description of the Prior Art
FIG. 25
is a circuit block diagram showing a memory cell array of a conventional nonvolatile semiconductor memory device such as a NOR flash memory.
Referring to
FIG. 25
, the so-called floating-gate memory cell transistors are arranged on the intersections between word lines WLn−1 to WLn+1 and bit lines BLn−1 to BLn+1. The word lines are connected with the gates of the memory cell transistors and the bit lines are connected with the drains of the memory cell transistors.
The sources of the memory cell transistors belonging to the same memory cell columns are connected to source lines SL in common.
(1) Overerased State of Flash Memory
An overerased state of the flash memory is now described.
If any cell present on a bit line has a depressed threshold voltage Vth (Vth<0), the threshold voltages Vth of all the remaining cells present on the bit line cannot be correctly measured in a flash memory having the aforementioned NOR array structure or an array structure referred to as a DINOR (divided bit line NOR) structure described later. In other words, it is difficult to perform a normal read operation as to the memory cells connected to this bit line.
When the threshold voltage Vth of the memory cell arranged on the intersection between the bit line BLn and the word line WLn is depressed in
FIG. 25
, for example, the threshold voltages Vth of the remaining cells present on the bit line BLn cannot be measured due to influence by the cell located on the intersection between the bit line BLn and the word line WLn even if the threshold voltages Vth of the remaining cells are enhanced (Vth>0). In other words, it follows that all threshold voltages Vth are measured as apparently not more than 0 V.
FIG. 26
illustrates apparent threshold voltage distribution of memory cell transistors including such an overerased memory cell.
FIG. 26
shows distribution of the number (bit number) of memory cells having thresholds Vth.
When investigating the distribution of the thresholds Vth in the memory cell array including the overerased memory cell (having the depressed threshold voltage Vth) as described above, cells proportionate to the number of cells present on the same bit line are determined as having threshold voltages Vth less than zero.
Therefore, the number of bits apparently corresponding to the threshold voltages Vth of zero corresponds to the sum of the memory cells coupled to the bit line including such an overerased memory cell, as shown in FIG.
26
.
Such a depressed cell can occur since electrons are accidentally excessively extracted from a floating gate in the flash memory.
(2) Repair Method for Overerased Cell
Some conventional methods of selectively returning the threshold of an overerased memory cell to an enhanced state are now described as methods of repairing the overerased memory cell after an erase operation.
In the following description, the operation of returning the threshold voltage Vth of the overerased cell to the enhanced state is referred to as “write-back”.
Some methods have been reported in relation to write-back processing.
(2-1) Method of Selecting Overerased Bit and Injecting Electrons in CHE Mode
A method employing channel hot electrons (hereinafter abbreviated as CHE) is known as one of methods of injecting electrons into the floating gate of the cell in the flash memory.
Writing with CHE is a method of injecting high-energy electrons accelerated beyond the barrier height of an oxide film into a floating gate FG among channel electrons accelerated by a steep electric field in the vicinity of the drain of the memory cell.
FIG. 27
is a schematic sectional view of a flash memory cell for illustrating write-back of an overerased bit with CHE.
Referring to
FIG. 27
, a gate oxide film
13
, a floating gate
14
consisting of polycrystalline silicon or the like, an insulating film
15
having a three-layer structure, referred to as an ONO structure, of an oxide film, a nitride film and an oxide film for preventing leakage and a control gate
16
consisting of polycrystalline silicon or the like are stacked on a P-type semiconductor substrate
11
. N-channel source and drain regions
12
a
and
12
b
are formed in a self-alignment manner in proximity to the aforementioned stacked gates on the P-type semiconductor substrate
11
.
A source voltage Vs, a drain voltage Vd, a control voltage Vcg and a substrate voltage Vsub are applied to the source region, the drain region, the control gate and the substrate
11
respectively. The control voltage Vcg is generally set higher than the drain voltage Vd.
The threshold voltage Vth of the memory cell can be enhanced by writing back the overerased cell in the CHE mode. However, the write-back in the CHE mode has the following problems:
First, the overerased cell must be selected. In other words, the write-back operation is performed after selecting the overerased cell, and hence the circuit structure for implementing selection of the overerased cell is disadvantageously complicated.
Second, a desired voltage for implementing the write-back operation in the CHE mode must be set between the drain and the gate. The desired voltage requires potential arrangement different from that bringing cell into a written state in general. The different potential arrangement is required since the width fluctuating the threshold voltage Vth of the memory cell to be written back is different from the fluctuation width in the conventional write operation.
Third, a channel current must be driven in write-back.
In order to drive the channel current, several 10 &mgr;A is required for each cell as the drain current Id of the memory cell transistor.
(2-2) Method of Self-Selectively Writing Back Overerased Bit
(2-2-1) Write-Back with Drain Avalanche Gate Current
The write-back operation in the CHE mode requires a circuit structure capable of selecting the overerased cell as described above.
A write-back method employing a gate current caused by drain avalanche hot electrons (hereinafter abbreviated as DAHE) or drain avalanche hot holes (hereinafter abbreviated as DAHH) is reported in “A Self-Convergence Erase for NOR Flash EEPROM Using Avalanche Hot Carrier Injection” by Yamada et al., IEEE Trans. Electron Devices, Vol. 43, p. 1937 (1996: hereinafter referred to as literature 1) as a method requiring no such bit selection.
A flash memory employing the CHE mode has a high P
+
substrate concentration (up to about 10
18
cm
−3
) and a dense N
+
diffusion layer (up to about 10
20
cm
−3
), in order to improve the efficiency of CHE. Spreading of a depletion layer is suppressed only in the P-type substrate region, for improving the CHE efficiency.
The aforementioned literature 1 also describes that the injection rate of As into the drain is 5×10
15
cm
−2
, and the concentration of the N
+
diffusion layer exceeds 10
20
cm
−3
after heat treatment under such injection condition.
FIG. 28
is a conceptual diagram showing dependency of logarithmic values of the drain current Id and the gate current Ig on a gate voltage Vg in the flash memory cell having such a drain structure.
As to the gate current Ig, is known that currents of DAHH, DAHE and CHE modes are observed in a gate voltage region where the channel current flows from the lower side of the gate voltage Vg as shown in FIG.
28
.
Such a state is described in the aforementioned literature
1
and other literature such as literature 2: “A Novel Floating-Gate Method for Measurement of Ultra-Low Hole and Election Gate Currents in MOS Transistors” by Y. Nissan-Cohen, J. Electron Device Letter, Vol. EDL. 7, No. 10, Octeber, pp. 561-563 (1986) or U.S. Pat. No. 5,546,340 or literature 3: “Failure Mechanisms of Flash Cell in Program/Erase Cycling” by P. Cappelletti et al., IEDM 94, pp. 291-294, for example

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