Nonvolatile semiconductor memory device capable of...

Details Nonvolatile semiconductor memory device capable of... Nonvolatile semiconductor memory device capable of...

1998-06-25

2001-06-26

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185170, C365S185190, C365S185230

Reexamination Certificate

active

06252798

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a NAND cell type nonvolatile semiconductor memory device using an electrically erasable memory cell with a floating gate electrode for accumulation of electric charge layered beneath a control gate electrode. More particularly, the memory cell includes plural memory cells connected in series. The invention also relates to a data writing control method in such a memory device.
Nonvolatile semiconductor memory devices are known that can be electrically erased and integrated to a high degree such as an EEPROM (electrically erasable programmable ROM). Specifically, a NAND cell type EEPROM connecting a plurality of memory cells in series is known as providing a high degree of integration. In such a NAND cell type EEPROM, the memory cell has a “stacked gate structure” in which a control gate electrode is laminated on a floating gate electrode over an insulation film on a semiconductor substrate. A plurality of memory cells are connected in series so that cells share sources and drains with adjacent cells. The string of series connected cells make up one unit connected to the bit line to constitute the NAND cell. The NAND cells are arranged in a matrix to make up the memory cell device.
The NAND cells are arranged along the column direction of the memory cell array and the drain of the end cell is connected to the bit line, which is the data line, through each selection gate electrode. The other end of the string of NAND cells is connected to the source line through the selection gate electrode and further to the common source line, which also provides the reference potential. The control gate electrode and selection gate electrode of each memory cell are connected in common along the row direction of the memory cell array,with the control gate electrodes connected to the word lines, and the selection gate electrodes connected to the selection gate lines.
When writing such a NAND cell type EEPROM, if a lower voltage operation can be achieved, the transistors that make up the column decode circuitry connected to the bit lines can be chosen to be V
CC
transistors. Conseqeuntly, the area of the peripheral circuit can be reduced. To achieve such a lower voltage operation, various technologies have proposed and adopted a “self-boost writing system,” thereby reducing the chip size. The operation of such a self-boost writing system is described below.
FIG. 19
is a diagram showing an equivalent circuit of a memory cell of this NAND cell type EEPROM. In the diagram, the symbol BL is a bit line, SG is a selection gate line, CG is a word line, and SL is a source line.
In the usual batch writing of plural pieces of data into plural memory cells along a row direction, writing starts from a memory cell at a position remote from the bit line BL.
In a random writing operation, arbitrary memory cells between bit line BL and source line SL are written randomly. When writing, 0V is first applied to the bit lines BL
1
to BLn of the NAND cell connected to the memory cell into which “0” data is to be written. Consequently, in the bit lines BL
1
to BLn of the NAND cell to which the memory cell to be written with “1” data is connected, the same voltage as the drain side selection gate voltage, a higher voltage, or a potential for sufficiently cutting off the drain side selection gate if lower than the drain side selection gate voltage is applied, so that write selection and non-selection (write disable) can be distinguished in the bit lines BL
1
to BLn.
In this state, when a potential for turning on the memory cell, that is, a write pulse voltage V
pp
or a transfer voltage pulse V
pass
of non-selection word line, is applied to all word lines CG
1
to CGn of the selection block, if a potential for turning on the memory cell is applied at a specified potential in the rise potential of the voltage pulse, OV is transferred to the channel of the NAND connected to the bit linesBL
1
to BL
2
for writing “0” data. Thus, when the write voltage pulse V
pp
is applied to the selection word lines CG
1
to CGn connected to the memory cell to be written with “0” data, “0” data is written into the selection memory cell connected to the selection bit lines BL
1
to BLn to which 0V has been applied.
In the channel of the NAND cells connected to the bit lines BL
1
to BLn to be written with “1” data, a specified initial potential, subtracting the threshold portion of the corresponding selection gate transistor from the potential of the bit lines BL
1
to BLn through the selection gate line SG
1
of the bit line side, is transferred from the bit lines BL
1
to BLn. The bit line side selection gate transistor is cut off and floats. At this time, in the source line SL, 0V or a specified positive potential is applied in order to cut off sufficiently the source side selection gate.
Here, the channel potential of the non-selection memory cell connected to the selection word line to which write voltage pulse V
pp
is applied, for writing in “1” data, that is, the memory cell cutting off the bit line side selection gate transistor, with the channel in the floating state, must be sufficiently large so that “0” may not be written in. That is, the threshold fluctuation of the non-selection memory cell should be within an allowable range. This is because, in this memory cell, the fluctuation of threshold is smaller when the difference of the write voltage pulse V
pp
and channel potential Vch is smaller.
On the other hand, the specified transfer voltage pulse V
pass
is applied to the non-selection word line not to be written in, and the potential of the channel is raised to a certain potential from the initial potential by utilizing the capacitance between the gates and their channels. Therefore, as the transfer voltage pulse V
pass
is greater, the threshold fluctuation of the memory is smaller.
Thus, this transfer voltage pulse V
pass
is also applied to the memory cells in which “0” data is not written, among the memory cells connected to the selection bit lines provided with 0V for the bit lines BL
1
to BLn. Therefore, the greater the transfer voltage pulse V
pass
, the less likely the threshold fluctuates. Considering these points, the minimum value and maximum value of the transfer voltage pulse V
pass
are determined.
Usually, this transfer voltage pulse V
pass
and write voltage pulse V
pp
are controlled by the “step-up system” for optimizing the specified initial voltage, the step voltage, the final voltage and the pulse width in order to narrow the distribution of the threshold for “0” data memory cells and to reduce writing errors.
To erase data, on the other hand, either “batch erase” for simultaneously erasing all memory cells in the NAND type cell, or “block erase” for erasing the cells in a specified by unit is selected. That is, in all or selected blocks, 0V is applied to all control gates, and in the case of block erase, a write voltage pulse V
pp
(for example, 20V) is applied to the control gate and selection gate of the non-selected blocks, and the bit line and source line are set in a floating state and a high voltage, for example, 20V is applied to the p-well. As a result, in all memory cells of all or selected blocks, electrons of the floating gate are released to the p-well, and the threshold moves in the negative direction. Furthermore, to read out data, a write voltage (for example, 4.5V) is applied to the selection gate transistors and word lines of non-selection memory cells other than the selection memory cells to turn them on, while 0V is applied to the word lines of the selection memory cells. At this time, by detecting the current flowing in the bit lines BL
1
to BLn, either “0” or “1” data is judged.
However, in the “self-boost writing method” conventionally used for the NAND cell type EEPROM, the following problems were known, and have required solution.
FIG. 20
is a diagram showing an equivalent circuit of a NAND cell type EEPROM including electrodes of memory cells in floating channel writing, and memory cell A and memory cell B

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