Nonvolatile semiconductor memory device and programming or...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S185290

Reexamination Certificate

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07460410

ABSTRACT:
In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.

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