Nonvolatile semiconductor memory device and nonvolatile...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S226000

Reexamination Certificate

active

07986557

ABSTRACT:
A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.

REFERENCES:
patent: 5663918 (1997-09-01), Javanifard et al.
patent: 6160440 (2000-12-01), Javanifard et al.
patent: 6370075 (2002-04-01), Haeberli et al.
patent: 6977842 (2005-12-01), Nazarian
patent: 2007/0040599 (2007-02-01), Sato
patent: 2009/0003103 (2009-01-01), Shimizu et al.

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