Nonvolatile semiconductor memory device and method of erasing st

Details Nonvolatile semiconductor memory device and method of erasing st Nonvolatile semiconductor memory device and method of erasing st

1994-12-16

1996-10-08

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518501, 36518911, 36518529, G11C 1134

Patent

active

055638244

ABSTRACT:
A source line of a memory array included in a flash memory is set to a 3V potential by a source line circuit, a power supply voltage of 6V is applied to a sense amplifier, and 3V is applied as the ground potential. After the setting of such potential conditions, reading of the memory array is performed. When current flows to the memory cells as a result of reading, it means that the memory cell has been erased. If the current does not flows through the memory cell, erasure pulse is applied again and every memory cell is verified.

REFERENCES:
patent: 5040147 (1991-08-01), Yoshizawa et al.
patent: 5341329 (1994-08-01), Takebuchi
patent: 5388069 (1995-02-01), Kokubo

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory device and method of erasing st does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory device and method of erasing st, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device and method of erasing st will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-62370