Nonvolatile semiconductor memory device and method of...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S230030, C365S185230, C365S185220, C365S185240

Reexamination Certificate

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07907446

ABSTRACT:
This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines.

REFERENCES:
patent: 7257032 (2007-08-01), Fujiu et al.
patent: 2006/0239070 (2006-10-01), Yen et al.
patent: 2007/0153577 (2007-07-01), Guterman
patent: 2008/0055985 (2008-03-01), Kanda
U.S. Appl. No. 12/491,638, filed Jun. 25, 2009, Futatsuyama et al.

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