Nonvolatile semiconductor memory device and method of...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185140, C365S185180, C365S185220

Reexamination Certificate

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07468917

ABSTRACT:
In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the selection memory cells, a gate voltage which increases step by step, until a threshold voltage of each of the selection memory cells reaches a target threshold voltage, such that the threshold voltage increases step-by-step.

REFERENCES:
patent: 6452837 (2002-09-01), Mori et al.
patent: 7088616 (2006-08-01), Tanaka et al.
patent: 7376019 (2008-05-01), Hashimoto et al.
patent: 7411819 (2008-08-01), Takeuchi
patent: 2001-52486 (2001-02-01), None
patent: 2003-123491 (2003-04-01), None
patent: 2005-235287 (2005-09-01), None

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