Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-01-22
2004-05-11
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06735125
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device wherein a high voltage is applied to a source of the nonvolatile semiconductor memory device during erasure and a method of erasing the same.
ETOX (brand name of an Intel product, abbreviation of EPROM Thin Oxide) is one of conventional flash memories i.e. batch erase type memories that are most widely used.
FIG. 8
shows a schematic cross sectional view of this ETOX-type flash memory cell. As shown in
FIG. 8
, a floating gate
5
is formed via a tunnel oxide film
4
on a source
1
, a drain
2
and a well of substrate
3
between the source and the drain. A control gate
7
is further formed on the floating gate
5
via an interlayer insulating film
6
.
The operation principles of the above ETOX-type flash memory are explained below. During a write operation, a voltage Vpp (for example, 10 V) is applied to the control gate
7
, a standard voltage Vss (for example, 0 V) is applied to the source
1
and a voltage of 6 V is applied to the drain
2
as shown in Table 1. Consequently, a large amount of current flows in a channel layer. Channel hot electrons are generated in a portion on the drain
2
side having a high electric field, and then electrons are injected into the floating gate
5
. As a result, the threshold voltage of the memory cell
8
is increased and data is written to the memory cell.
FIG. 9
shows a threshold voltage distribution in a written i.e. programmed state and an erased state. As shown in
FIG. 9
, the threshold voltage of the written memory cell becomes 5 V or higher.
TABLE 1
Control gate 7
Drain 2
Source 1
Substrate 3
Write
10 V
6 V/0 V
0 V
0 V
Erase
−9 V
Open
5 V
0 V
Read
5 V
1 V
0 V0
0 V
Furthermore, during an erase operation, a voltage Vnn (for example, −9 V) is applied to the control gate
7
and a voltage Vpe (for example, 5 V) is applied to the source
1
to open the drain
2
as shown in FIG.
10
. Consequently, a strong electric field is generated in the tunnel oxide film
4
between the source
1
and the floating gate
5
. Then, electrons are pulled to the source
1
side by Fowler-Nordheim (FN) tunneling to decrease the threshold voltage of the memory cell
8
. As a result, the threshold voltage of the erased memory cell
8
becomes 1.5 to 3 V as shown in FIG.
9
.
Furthermore, during a read operation, a voltage of 1 V is applied to the drain
2
while a voltage of 5 V is applied to the control gate
7
. Here, when the memory cell
8
is in an erased state and therefore its threshold voltage is low, a current flows into the memory cell
8
and a state “1” is determined. On the other hand, when the memory cell
8
is in a written state and therefore its threshold voltage is high, a currents does not flow into the memory cell and a state “0” is determined.
Based on such operation principles, the write, erase and read operations are performed in the memory cell
8
.
The method of erasing the flash memory is hereinafter referred to as a conventional erase method
1
.
In an actual erase operation in a nonvolatile semiconductor memory device, batch erasure is performed in units of relatively large blocks, for example, 64 kB. In this case, since threshold voltages of memory cells in the block to be erased may be in a written state or an erased state, a complicated algorithm is used for the batch erasure. A basic algorithm of the conventional erase method
1
is shown in FIG.
11
. This batch erasure algorithm is briefly explained below.
When an erase operation is started, a write-before-erase operation is first performed in all the memory cells to prevent overerasure in step S1. That is, pulses having a prescribed width as write-before-erase pulses are applied to the control gate
7
and the drain
2
of a memory cell
8
. In step S2, a write-verify operation is performed. That is, the threshold voltage value of each memory cell
8
is verified. In step S3, whether the verify result is acceptable, that is, whether the threshold voltage values of all the memory cells are a prescribed value (5.0 V) or higher, the voltage for a written state, is judged. As a result, when the result is unacceptable, the operation goes back to the aforementioned step S1 and the write-before-erase operation is repeated. On the other hand, when the result is acceptable, the operation proceeds to step S4. Thus, until the threshold voltages of all the memory cells in a block to be erased become the prescribed value or higher, the write-before-erase pulse application and the verify operation are repeated.
In step S4, erase pulses are applied. In this erase pulse application, to prevent overerasure (excessive erasure, which means in the case of
FIG. 9
that a threshold voltage value of a memory cell becomes 1.5 V or lower), the pulse width of the erase pulses is set to be shorter than time required for complete erasure (for example, 10 ms) and pulses are applied to the control gate
7
and the source
1
in a memory cell to be erased in units of word lines in a batch.
In step S5, an erase-verify operation is performed. That is, the threshold voltage value of each memory cell
8
is verified. In step S6, whether the verify result is acceptable, that is, whether the threshold voltage values of all the memory cells are a prescribed value (3.0 V) or lower representing an erased state, is judged. As a result, when the result is unacceptable, the operation goes back to the aforementioned step S4 and the erase pulses application is repeated. On the other hand, when the result is acceptable, the operation proceeds to step S7.
The erase-verify operation in the above step S5 is the same as the read operation in Table 1 except that a voltage of 3.0 V is applied to the control gate
7
via a word line. That is, a voltage of 3.0 V is applied to a word line of a selected memory cell to be verified while 0 V is applied to word lines of the other unselected memory cells. Then, a verify operation is performed by successively selecting a word line and detecting whether a cell current flows into a memory cell. Alternatively, a voltage of 5.0 V is applied to a word line and its current level is compared with that of a memory cell having a threshold voltage of 3.0 V. Then, if there is at least one memory cell having the prescribed threshold voltage or higher, erase pulses are applied again. Thus, until the threshold voltages of all the memory cells in the block to be erased become a desired value or lower, the erase pulse application and the verify operation are repeated.
In step S7, an overerase-verify operation is performed to verify existence an overerased memory cell. In step S8, whether the verify result is acceptable is judged. As a result, if at least one overerased memory cell is detected, the operation proceeds to step S9. If not, the erase operation is terminated. In step S9, a soft program (light-level write) is performed in the overerased memory cell. Thus, the threshold voltage of the overerased memory cell is increased. When it is determined in the aforementioned step S8 that the threshold voltage distributions of all the memory cells fall in the range of 1.5 to 3.0 V, the erase operation is terminated.
Usually, an erase characteristic of the memory cell
8
varies as shown in FIG.
12
and there are memory cells wherein the erase operation is fast performed (fast cells) and memory cells wherein the erase operation is slowly performed (slow cells).
FIG. 12
shows that, when erase pulses are applied for 300 ms in total, the threshold voltage of the fast cell becomes 3 V which is the upper limit voltage of the erased state and that the threshold voltage of the slow cells becomes 1.5 V which is the lower limit voltage of the erased state.
However, the variation in the erase characteristic of the memory cell
8
is further increased, and the overerasure is progressed. In particular, if there is a memory cell of which threshold voltage is 0 V among unselected memory cells and there is a memory cell of which threshold voltage is 0 V or lower, a cell
Ho Hoai
Morrison & Foerster / LLP
LandOfFree
Nonvolatile semiconductor memory device and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory device and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3228752