Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2008-04-29
2008-04-29
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000, C438S130000, C438S275000, C438S278000, C438S290000, C257S314000, C257S315000, C257S390000, C257SE21688
Reexamination Certificate
active
11302203
ABSTRACT:
A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
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Aritome Seiichi
Goda Akira
Hazama Hiroaki
Iizuka Hirohisa
Moriyama Wakako
Ahmadi Mohsen
Kabushiki Kaisha Toshiba
Lebentritt Michael
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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