Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-07-13
2001-11-06
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185120
Reexamination Certificate
active
06314022
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing a same and, more particularly, to the nonvolatile semiconductor memory device used as a one-chip microcomputer-mixed flash memory and the method for manufacturing the same.
2. Description of the Related Art
A nonvolatile semiconductor memory device has conventionally been known in which a plurality of memory cells is connected in parallel with each other each of which has a memory transistor and a selecting transistor which are connected in series between a bit line and a source electrode, in such a configuration that information is, via the bit line, input to and output from one of these memory cells which is selected by a word line connected to gate electrodes of these two transistors. As shown in
FIG. 9
, a flash memory (nonvolatile semiconductor memory device)
1
includes a word line WLn and a main bit line MBLn, which is in turn connected via a block selecting transistor BST to a sub-bit line SBLn.
Memory cells
1
a
which form the flash memory
1
are arrayed in a two-transistor type construction for high-speed read-out operations, wherein each of the memory cells
1
a
has a memory transistor
2
and a selecting transistor
3
which are connected in series between the bit line and a source electrode thereof, so that information may, via the bit line, be input to and output from a memory cell
1
a
selected by a word line WLn.
The memory transistor
2
and the selecting transistor
3
both have their gate electrode connected to the word line WLn, while the memory transistor
2
has its drain and source connected to the sub-bit line SBLn and the selecting transistor
3
respectively. The main bit line MBLn is connected via a Y-address selector
4
to a sense-amplifier (SA)
4
a.
As shown in
FIG. 10
, in the memory cell
1
a
, its memory transistor
2
is positioned on a side of the drain D, that is, each pair of the memory transistors
2
is arranged so as to sandwich a contact hole
5
, through which the memory cell
1
a
is connected to the bit line. Outside of each of these memory transistors
2
, the selecting transistor
3
is positioned. Note here that a dotted line in the
FIG. 10
indicates a region which encloses one memory cell.
As shown in
FIG. 11
, on a silicon substrate
6
are formed side by side the memory transistor
2
and the selecting transistor
3
of the memory cell
1
a
. These two transistors make up in combination one memory cell
1
a
for storing one bit of data.
In a well
6
a
formed in the silicon substrate
6
are provided a source region S connected to ground (not shown) and a drain D connected to the bit line, between which are formed two channel regions.
The memory transistor
2
and the selecting transistor
3
each have a floating gate FG provided on the silicon substrate
6
with a gate oxide film therebetween and a control gate CG provided on the floating gate FG with an Oxide Nitride Oxide (ONO) film therebetween. The floating gate FG and the control gate CG of the selecting transistor
3
are short-circuited at a predetermined portion (not shown).
Since the memory transistor
2
and the selecting transistor
3
are formed concurrently, they have same parameter values such as a channel width W, a channel length L, a gate film thickness tox, or a like. That is, the two transistors of the memory cell
1
a
, memory transistor
2
and the selecting transistor
3
have a same channel width (see FIG.
10
).
A typical example of read-out operations is described below of such two-transistor type flash memory.
As shown in
FIGS. 12A
,
12
B and
12
C, in read-out operations, in such a state that 1.0 [V] is applied to the drain D, 2.5 [V] is applied to gate G of the memory transistor
2
(control gate voltage: Vcg), 2.5 [V] (constant) is applied to the gate G of the selecting transistor
3
, and 0.0 [V] is applied to the well W (see FIGS.
12
A and
12
B), a sense-amplifier (not shown) detects a larger drain current Id when an erased state (threshold=1.0 [V]) is read out and a smaller drain current Id when a written-in state (threshold=5.0 [V]) is read out (see FIG.
12
C), to decide “0” and “1” respectively.
These written-in and erased states are, as described above with reference to read-out operations, discriminated from each other based on a difference in threshold of the memory transistor
2
, that is that in the written-in state is 5.0 [V] and that in the erased state is 1.0 [V]. This difference in the threshold is given by changing an amount of charge stored in a floating gate.
The more negative charge stored in the floating gate, the threshold rises higher, while more positive charge stored therein, the the threshold falls lower. That is, in the above-mentioned case, a write-in operation equals to inject electrons into the floating gate, while an erasure operation equals to release the electrons stored in the floating gate. This method for injecting/releasing electrons may be a method of utilizing an FN current via a gate oxide film and an ONO film or a method of using a hot carrier.
Note here that in such a flash memory
1
as described above, larger a read-out current in an erased state, higher is a read-out speed (access speed), so that to enhance access speed, the read-out current needs to be increased.
As shown in
FIG. 13
, if, to read out the memory cell
1
a
, for example, about 1.0 [V] is applied to the drain D and a power supply voltage of 2.5 [V] is applied to the gates of the memory transistor
2
and the selecting transistor
3
, voltages applied between the source and the drain of each of the transistor
2
and transistor
3
are divided so as to total to 1.0 [V]. Therefore, assuming a the source-drain voltage of the selecting transistor
3
to be Vc [V], that of the memory transistor
2
is (1−Vc) [V].
With this, the memory transistor
2
and the selecting transistor
3
are separated from each other, so that the source-drain voltage of the selecting transistor
3
is varied from 0.0 [V] to 1.0 [V] to check its properties (see FIG.
13
), thus measuring a read-out current I flowing through the memory transistor
2
and the selecting transistor
3
.
As shown in
FIG. 14
, the read-out current I through the selecting transistor
3
increases as variable voltage Vc rises, while that through the memory transistor
2
is at a maximum when the variable voltage Vc is 0.0 [V] and stops flowing when it is 1.0 [V], that is 0.0 [V] is applied between the source and the drain.
Therefore, an intersection of a load curve of the memory transistor
2
and that of the selecting transistor
3
provides an operating point P of the memory cell
1
a
, so that a voltage of v
1
[V] is applied to the memory transistor
2
and a voltage of v
2
[V], to the selecting transistor
3
, thus flowing a read-out current (turn-on current) I which corresponds to that operating point P.
However, since the memory transistor
2
and the selecting transistor
3
are formed on a same substrate, a resultant substrate-bias effect of the memory transistor
2
decreases driving force of the memory transistor
2
, thus naturally reducing the read-out current I.
If, in this case, as shown in FIG.
15
A and
FIG. 15B
, in a transistor (see FIG.
15
A), when, for example, a constant voltage of 1.0 v is applied as drain voltage V
D
and 2.5 v is applied as control gate voltage V
g
, threshold voltage V
th
of this transistor is as follows:
V
th
=2&phgr;
f
+V
FB
+[2&egr;qN (2&phgr;
f
+V
BS
)]
½
·1/C
o
That is, as a voltage is applied to the source, the threshold voltage of the tansistor rises apparently (see FIG.
15
B).
Consequently, the current I
d
is as follows:
I
d
=(W/L)·&mgr;
eff
·C
ox
[(V
GS
−V
th
)V
DS
−(½)·
Kawata Masato
Tashiro Tsutomu
Hoang Huan
NEC Corporation
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