Nonvolatile semiconductor memory device and method for...

Details Nonvolatile semiconductor memory device and method for... Nonvolatile semiconductor memory device and method for...

2002-01-22

2003-12-02

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185280, C365S185290

Reexamination Certificate

active

06657893

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a method for driving the same. More particularly, the present invention relates to a nonvolatile semiconductor memory device functioning as a flash EEPROM employing a two-layer gate electrode structure including floating gate and control gate electrodes and to a method for driving the same.
In recent years, a flash EEPROM is increasingly required to perform a rewrite operation using a single power supply at a low voltage and a high-speed read operation at a low voltage. A “low voltage” herein refers to about 1.5 V to about 3.3 V.
Various types of flash EEPROMs are now available. For example, a flash EEPROM developed by a certain corporation injects channel hot electrons (CHE) from a drain into a floating gate electrode while writing, and ejects the electrons out of the electrode into a source by using FN tunneling current while erasing. Hereinafter, a flash EEPROM of this type will be called a “CHE-type flash EEPROM”. The CHE-type flash EEPROM is advantageous in that the circuit configuration and fabrication process thereof can be implemented by extending EPROM technologies. However, since current of about 500 &mgr;A should be consumed per cell for writing, a rewrite operation using a single power supply at 5 V can be performed relatively easily. But a rewrite operation using a single power supply at 2.5 V or less is hard to realize.
Another flash EEPROM, ejecting electrons out of a floating gate electrode into a drain while writing and injecting electrons into the floating gate electrode while erasing by using, in both operations, FN tunneling current over the entire surface of a channel, has prevailed in the art recently. Examples of flash EEPROMs of this type include a DINOR-type flash EEPROM disclosed in U.S. Pat. No. 5,283,758 and an AND-type flash EEPROM disclosed in U.S. Pat. No. 5,592,415. Flash EEPROMs of those types use the FN tunneling current for both writing and erasing. Accordingly, the level of current required for writing and erasing may be low and therefore a rewrite operation can be performed using a single power supply at a low voltage (e.g., 2.5 V). Hereinafter, a flash EEPROM of such a type will be called a “drain-side FN-FN type flash EEPROM”.
A memory cell structure for a drain-side FN-FN type flash EEPROM and a method for driving the same will be described, and the problems thereof will be clarified. And then another conventional nonvolatile semiconductor memory device and a method for driving the same will be described as an exemplary means for solving the problems. It is noted that the drain-side FN-FN type flash EEPROM exemplified below is supposed to be a DINOR-type flash EEPROM.
First, a memory cell structure for a drain-side FN-FN type flash EEPROM and a method for driving the same will be described.
FIG. 24
is a cross-sectional view illustrating an exemplary memory cell structure for a drain-side FN-FN type flash EEPROM. As shown in
FIG. 24
, the memory cell includes: a P-type semiconductor substrate
101
; a deep N-type well
102
; a P-type well
103
; a gate insulating film
104
; a floating gate electrode
105
; an interelectrode insulating film
106
; a control gate electrode
107
; a drain diffusion layer
108
; and a source diffusion layer
109
.
The flash EEPROM shown in
FIG. 24
has fundamentally the same memory cell structure as that of the CHE-type flash EEPROM, but is somewhat different from the latter in the shapes of the diffusion layers. Specifically, in a memory cell of the CHE-type flash EEPROM, a source diffusion layer is deeper than a drain diffusion layer. Conversely, in a memory cell of the drain-side FN-FN type flash EEPROM, the drain diffusion layer
108
is deeper than the source diffusion layer
109
. This structural difference comes from the locations of the tunneling current utilized by the flash EEPROMs of these two types. That is to say, the CHE-type flash EEPROM uses the tunneling current flowing between the source diffusion layer and the floating gate electrode, whereas the drain-side FN-FN type flash EEPROM uses the tunneling current flowing between the drain diffusion layer
108
and the floating gate electrode
105
.
Next, the array structure of the drain-side FN-FN type flash EEPROM and an erasing method thereof will be described. FIG.
25
(
a
) is an electric circuit diagram illustrating voltages applied for simultaneously erasing data from all the memory cells in the drain-side FN-FN type flash EEPROM as a conventional nonvolatile semiconductor memory device. And FIG.
25
(
b
) is a cross-sectional view illustrating how electrons move during the erase operation.
First, the array structure of the drain-side FN-FN type flash EEPROM will be described with reference to FIG.
25
(
a
). As shown in FIG.
25
(
a
), each memory word line M.W-
0
,
1
,
2
interconnects the control gate electrodes
107
of memory cells arranged on the same row in the direction X. Each source line S-
0
,
1
,
2
interconnects the source diffusion layers
109
of memory cells arranged on the same row in the direction X. And each bit line B-
0
,
1
,
2
interconnects the drain diffusion layers
108
of memory cells arranged on the same column in the direction Y.
In this manner, the source lines are disposed in parallel to the word lines for memory cells (i.e., the memory word lines) and the bit lines are disposed vertically to the memory word lines.
Next, an erasing method will be described. FIG.
25
(
a
) illustrates the voltages applied for simultaneously erasing data from all of the nine memory cells illustrated. As shown in FIG.
25
(
a
), a voltage of +7 V is applied to the memory word lines M.W-
0
,
1
,
2
and a voltage of −7 V is applied to the P-type well PW. As a result, the potential difference between the control gate electrode
107
and the surface of the channel is 14 V at every memory transistor. Consequently, as shown in FIG.
25
(
b
), tunneling current flows from the entire surface region of the channel into the floating gate electrode
105
, whereby electrons are injected into the floating gate electrode
105
. In this case, the threshold voltage of the memory transistor is about 4 V.
Next, a writing method will be described. FIG.
26
(
a
) is an electric circuit diagram illustrating voltages applied for writing data into only one memory cell located at the center of the array and selected from the nine memory cells included in the drain-side FN-FN type flash EEPROM. And FIG.
26
(
b
) is a cross-sectional view illustrating how electrons move during the write operation. As shown in FIG.
26
(
a
), a voltage of −9 V is applied to the memory word line M.W-
1
connected to the memory cell to which data is selectively written (i.e., a selected memory cell). And voltages of +5 V and 0 V are respectively applied to the bit line B-
1
connected to the selected memory cell and to the P-type well (PW)
3
. As a result, the potential difference between the control gate electrode
107
and the drain diffusion layer
108
is 14 V at the selected memory cell. Consequently, as shown in FIG.
26
(
b
), tunneling current flows from the floating gate electrode
105
into the drain diffusion layer
108
and electrons are ejected out of the floating gate electrode
105
. In this case, the threshold voltage of the memory transistor is about 1.2 V.
Also, in order to prevent the data from being erroneously written into non-selected memory cells, a voltage of 0 V is applied to the other memory word lines M.W-
0
,
2
and to the other bit lines B-
0
,
2
. As a result, the potential difference between the control gate electrode
107
and the drain diffusion layer
108
can be no greater than 9 V at the non-selected memory cells and it is possible to prevent the data from being erroneously written into the non-selected memory cells.
Next, a reading method will be described. FIG.
27
(
a
) is an electric circuit diagram illustrating voltages applied for reading data from only one memory cell located at the center

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