Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-11-29
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
06219280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device having an erase verify circuit for a memory cell, and an erase verify method using the erase verify circuit.
2. Description of the Prior Art
At present, various electronic devices use erasable nonvolatile semiconductor memory devices (EEPROMs) , and the EEPROMs are increasing in capacity and integration degree. However, it is difficult to manufacture all memory cells constituting such EEPROM perfectly without any defects, and the defects greatly reduce the yield. To prevent this, manufacturers provide recent large-scale semiconductor memory devices with spare memory cells (to be referred to as redundant memory cells) , and set the devices such that a defective memory cell is switched to a redundant memory cell in the wafer inspection step, thereby obtaining high yield. In the wafer inspection step, an EEPROM is inspected by checking whether the circuit current or leakage current satisfies the prescribed standard or reads/writes are normally done, similar to semiconductor memory devices such as a DRAM and SRAM. The EEPROM stores data in accordance with the amount of electrons injected into the floating gate. Unlike the DRAM and SRAM, the EEPROM must be tested for additional inspection items such as whether electrons are normally injected into the floating gate or normally extracted. If a defective memory cell is detected as a result of the inspection, the address of the defective memory cell is stored in a fuse, EEPROM cell, or the like, and the defective memory cell is replaced with a redundant memory cell upon an access to this address.
Of EEPROMs, a flash type nonvolatile semiconductor memory device (to be referred to as a flash memory) has a function of erasing data of all memory cells at once or erasing data of memory cells grouped into a plurality of blocks in units of a predetermined number of blocks. In general, an erase operation is done by applying a high voltage between the gate and semiconductor substrate and flowing an FN (Fowler-Nordheim) tunnel current through a gate oxide film interposed between them. The FN tunnel current varies depending on the film thickness or quality of the gate oxide film or the voltage applied. For example, a large tunnel current flows through a memory cell having a thin gate oxide film to degrade its film quality. Low film quality of the gate oxide film degrades the charge holding characteristic of the floating gate, and the memory contents change over time. If electrons are excessively extracted from the gate, the memory cell is over erased and a current flows even if the cell is not selected. To solve these problems, the flash memory executes memory cell erase operation not all at once but divisionally several times, and gradually erases data while confirming the erase condition. This confirmation operation is called erase verify. The boundary between erase and over erase is called a repair level, the operation of confirming whether a memory cell is over erased is called repair check. An over erased memory cell undergoes write-back processing so as to inject electrons to a predetermined electron injection amount. Verify operation in erase verify and write-back processing is performed by confirming whether the threshold level of a memory cell falls within a predetermined level range. More specifically, a predetermined voltage is applied to the gate of a memory cell, and whether a predetermined current flows is confirmed.
The flash memory must undergo the above-described stepwise erase and erase verify operations even after the memory is assembled into an electronic device. For this purpose, the flash memory itself incorporates a circuit for performing erase verify and repair check, and automatically executes erase operation, erase verify, and repair check (to be referred to as automatic erase processing) in accordance with an erase command or the like supplied from a microprocessor or the like. In an erase of the flash memory, it is checked by erase verify whether all memory cells subjected to an erase reach a predetermined threshold level or less. If even one memory cell does not satisfy this condition, erase processing and erase verify processing are repeated again. When all memory cells reach a level equal to the predetermined threshold level or less, the flash memory informs the microprocessor or the like of the completion of the erase. Also for write operation, write verify may be performed according to the above method, but can be omitted by excessively injecting electrons into a memory cell for storing binary information. The write, erase, and their verify processes are the same even after the flash memory is assembled in an electronic device or in the wafer inspection step.
FIG. 1
is a flow chart showing automatic erase verify processing S
400
in a conventional flash memory. First, in a step which is not shown, data is written in all memory cells in order to make the amounts of electrons injected in all the memory cells uniform. Then, a predetermined voltage is applied to the control gates and semiconductor substrates (channels) of all the memory cells to erase data (S
401
). In this erase processing, as is well known, electrons which had come to be present in the floating gate of a memory cell upon the write processing are extracted to the semiconductor substrate side by an FN current by applying the voltage, thereby decreasing and the threshold level of the memory cell. After that, the start address of a memory cell subjected to an erase is set for the erased memory cell (S
402
), the threshold level of the memory cell at this address is detected, and whether an erase is properly done is verified (S
403
). If “Pass” in step S
403
, whether the address is the last address of the target erase area is checked (S
404
). If NO in step S
404
, the address is incremented (S
405
), and the same verify is executed for all memory cells. Verify is done up to the last address (S
406
) to complete the erase verify. If “Fail” in step S
403
, the flow returns to the erase step of step S
401
again to repeat the same erase verify processing.
More specifically, memory cells vary in characteristic and are set for the above-described reason such that their data cannot be completely erased by one erase operation. Thus, an unerased memory cell (fail cell) or cells is or are detected. Erase processing is therefore performed again for all memory cells. By this erase processing, an erase voltage is applied again to each memory cell, electrons in the floating gate of the memory cell are further extracted, and the threshold level of the memory cell further drops. As a result, a memory cell which has not reached a predetermined threshold level in a previous erase reaches the predetermined threshold level by the current erase, and it ceases to be a fail cell. When all memory cells reach the predetermined threshold level or less by repeating this processing, verify ends. Note that repair check may be done in step S
403
, and a memory cell from which electrons are excessively extracted may undergo write processing to return the memory cell to the threshold level.
In this erase verify method, however, when memory cells include some memory cells (to be referred to as peculiar memory cells, exhibiting high threshold levels, erase verify is repeated in the above fashion until the threshold levels of the peculiar memory cells drop to a predetermined level. This prolongs the erase verify processing time. In this case, the peculiar memory cells include a defective memory cell and a cell which requires a long time for an erase because electrons are difficult to extract from it. By repeating erase verify in this way, electrons in the floating gate of a normal memory cell are excessively extracted. The threshold level of the memory cell lowers the repair level to over erase the memory cell, or becomes negative to again over erase the memory cell.
FIG. 2
is a graph sh
NEC Corporation
Nelms David
Tran M.
Young & Thompson
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