Nonvolatile semiconductor memory device and data erase...

Details Nonvolatile semiconductor memory device and data erase... Nonvolatile semiconductor memory device and data erase...

2002-12-23

2003-12-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189070, C365S185220, C365S185180

Reexamination Certificate

active

06657898

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a data erase method therefor. The nonvolatile semiconductor memory device typically refers to a flash memory.
As shown in
FIG. 1
, a flash memory cell, which is most commonly used as a nonvolatile semiconductor memory device, includes a source
11
and a drain
12
formed distantly from each other on a substrate (well)
10
surface and a tunnel oxide film
13
, floating gate FG, interlayer insulating film
14
and control gate CG successively formed on the substrate
10
between these source and drain.
An operation principle of a flash memory of this type is described below. At the time of a write (also referred to as “program”) operation, Vpp (for example, 9 V) is applied to the control gate CG, a standard voltage Vss (for example, 0 V) is applied to the source, and a voltage of 5 V is applied to the drain as shown voltage conditions in the following Table 1. While 5 V is applied to the drain of a cell to which data is actually written, 0 V is applied to the drain of a cell to which data is not written. Consequently, a large amount of current flows in a channel layer, and hot electrons are generated in a portion on the drain side that has a high electric field. These electrons are implanted into the floating gate FG, and a threshold voltage is raised as in a written state distribution shown in FIG.
2
.
TABLE 1
Conventional example (1): Applied voltages in each mode
Control
Substrate
gate
Drain
Source
(well)
Write
9 V
5 V/0 V
0 V
0 V
Erase
−9 V  
Open
6 V
0 V
Read
5 V
1 V
0 V
0 V
Furthermore, as shown in
FIG. 3
, at the time of an erase operation, Vnn (for example, −9 V) is applied to the control gate CG, Vpe (for example, 6 V) is applied to the source, electrons are pulled from the floating gate FG to the source side, and a threshold voltage is lowered as in an erased state distribution as shown in FIG.
2
. As shown in
FIG. 3
, a BTBT (Band To Band Tunneling) current flows at the time of this erase operation. When this current is generated, hot holes and hot electrons are generated at the same time. Of these, the hot electrons flow into the drain, but, on the other hand, the hot holes are pulled to the side of the tunnel oxide film and trapped in the tunnel oxide film. It is generally said that this phenomenon deteriorates reliability.
At the time of a read operation, 1 V is applied to the drain, and 5 V is applied to the control gate CG as shown in the voltage conditions in Table 1. Since a current flows into a cell when a threshold voltage of a memory cell is low, that is, in an erased state, data in the memory cell is determined as “1”. On the other hand, since a current does not flow into the cell when the threshold voltage of the memory cell is high, that is, in a written state, data of the memory cell is determined as “0”.
Write, erase and read operations are performed by using such operation principles, but, in an actual device, an erase operation is performed in relatively large units such as, for example, in units of blocks such as 64 kB (kilobytes). At this time, since some of memory cells in a block from which data is to be erased are in a written state and others are in an erased state, the present applicants has proposed such a method of erasing data as shown in
FIG. 4
(Japanese Patent Laid-Open Publication No. 9-320282) so that data can be appropriately erased from these memory cells having different threshold voltages in a batch.
To make a threshold voltage distribution after an erase operation compact and prevent an overerased state (having a threshold voltage of 0 V or lower), first, a usual write operation (write-before-erase operation) is performed by channel hot electrons (S
1
) as shown in FIG.
4
. Consequently, all the cells are once in a written state having a threshold voltage 5 V or higher. At this time, for example, in a device having a power source of 5 V (5-V power source version), 8 memory cells can be operated simultaneously. When write time of one memory cell is 2 &mgr;s, time required for this operation is as follows:
2
&mgr;s×
64×1024×8/8=131 ms
This value accounts for about 20% when time required for execution of all the processing in
FIG. 4
(referred to as “total data erase time”) is 600 ms.
A voltage required for a write operation is generated by raising a voltage from the power source by using a charge pump circuit. However, since an ability of current supply from the charge pump is lowered in a 3-V power source version, which has a low power source voltage, the number of cells to which data can be simultaneously written is limited in a write method using channel hot electrons with a high write current per cell. While data can be simultaneously written to 8 memory cells in the 5-V power source version, the number of memory cells to which data can be simultaneously written is limited to 4 in the 3-V power source version. Consequently, time required to a write-before-erase operation is twice as long (that is, 262 ms). This problem becomes further marked as the power source voltage is made lower.
Subsequently, whether the write-before-erase operation is normally performed is verified (this operation is referred to as “verify operation after write-before-erase”) (S
2
). That is, whether the threshold voltage of a memory cell is 5.0 V or higher is verified in units of 8 bits. Since this operation is also performed in units of 8 memory cells, about the following time is required.
100 ns×64×1024×8/8=6.6 ms
Subsequently, an actual erase operation is performed, that is, an erase pulse is applied (S
3
). At this time, the erase pulse is applied in a batch of blocks. As described above, a BTBT current is generated, and a relatively high current flows. The total time required for this pulse application is about 300 ms, which accounts for about 50% of the total data erase time. Current consumption per cell is about 10 nA even with the addition of the BTBT current since the erase operation is performed by utilizing the FN tunneling phenomenon. Therefore, the following is obtained:
10 nA×64×1024=10 nA×64 kB=5.24 mA
Here, to reduce the erase pulse application time, it is sufficient to raise a voltage applied to the source. However, when the source voltage is raised, the BTBT current is increased, and holes trapped in the tunnel oxide film are increased. As a result, reliability is deteriorated due to the change of the threshold voltage. Accordingly, the source voltage cannot be further raised, and hence reduction of the erase pulse application time is limited.
Finally, whether an erase operation is normally performed is verified (referred to as “verify-after-erase operation”) (S
4
). That is, whether a threshold voltage of memory cell is 3.0 V or lower is verified.
Thus, there are problems in a general flash memory that a) the total data erase time is long and that b) current consumption is high. Causes for the problem a) of the long total data erase time include long time required for a write-before-erase operation performed for all memory cells, long time required for a verify operation after write-before-erase and limited reduction of erase pulse application time. Causes for the problem b) of the high current consumption include very high current consumption of 500 &mgr;A as a peak value of a write current per cell since the write-before-erase operation is performed by using channel hot electrons and a flow of the BTBT current, which is allowed at the time of erase pulse application.
Accordingly, there has been proposed a method of writing data to a memory cell having a structure shown in
FIG. 1
in a batch by utilizing the FN (Fowler-Nordheim) tunneling phenomenon for the write-before-erase operation (Japanese Patent Laid-Open Publication No. 6-96592 and Patent Application No. 2000-025779). Voltage conditions in each mode used for write, erase, write-before-erase and read operations are shown in the following Table 2 (Patent Ap

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