Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-11-28
2006-11-28
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230, C365S185290
Reexamination Certificate
active
07142458
ABSTRACT:
To provide a nonvolatile semiconductor memory device in which a disturb voltage onto a non-selected memory cell in writing operation is lessened, a nonvolatile semiconductor memory device, includes: a memory cell array equipped with a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines; a word line control circuit to control the plurality of word lines; and a line control circuit to control the plurality of bit lines and the plurality of source lines. Each of the plurality of memory cells is equipped with a gate electrode, a first impurity region, a second impurity region, and an electron trap region, which is positioned between the gate electrode and a substrate, and is formed at least at the first impurity region side of both the first impurity region and second impurity region. At the time when a writing operation is performed for a selected memory cell, the word line control circuit provides a selected word line connected to the selected memory cell with a selection voltage, provides a non-selected word line with a first mis-erasing prevention voltage, and provides a source line that is not connected to the selected memory cell with a second mis-erasing prevention voltage.
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Lam David
Seiko Epson Corporation
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