Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-08-24
2003-03-04
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S218000
Reexamination Certificate
active
06529415
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a nonvolatile rewritable semiconductor memory device.
2. Description of the Related Art
In nonvolatile semiconductor memory devices in which data can be erased and rewritten, a time length required for data erasure is relatively long in an initial state immediately after the shipping out from the factory. With repeated writing and erasing of data performed thereafter, the time length required for data erasure tends to settle at a relatively short time length.
FIG. 1
is a drawing showing the relationship between the number of cycles of data writing and erasure and the time length required for data erasure.
In
FIG. 1
, the horizontal axis shows the number of cycles of data writing and erasure, and the vertical axis shows the time length required for erasing one sector. Data is obtained with respect to product samples. Since there is a product variation in terms of characteristics thereof, a plurality of characteristic curves are plotted in the figure. As shown in
FIG. 1
, erasure of one sector takes approximately 1.5 seconds in an initial state, whereas erasure of one sector takes only 0.3 to 0.4 second after repeating the cycles of data writing and erasure approximately 100 times. Thereafter, the erasure time stays relatively short regardless of the number of cycles of subsequent data writing and erasure.
Because of the characteristics of the nonvolatile semiconductor memory devices as described above, the manufacturers need to guarantee their products by specifying the longest erasure time in the initial state. When the erasure time becomes shorter after the use of products, therefore, the guaranteed erasure time ends up being excessively long compared to the actual erasure time.
In order to make the erasure time settle at a relatively short length at a user end, the user has to manually repeat automatic erasure operations many times in order to repeat rewriting of data where the automatic erasure operation is defined as an operation that performs preparatory data writing prior to an erasure operation and then performs the erasure operation. This is a troublesome task in a practical sense. The manufacturers, on the hand, can repeat automatic erasure operations many times by use of a device tester, a handler, or the like. This will result in a significant drop in production efficiency because of the time and labor required for such a task.
Accordingly, there is a need for a nonvolatile semiconductor memory device that can set an erasure time to a relatively short stable time length.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a nonvolatile semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a nonvolatile semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a nonvolatile semiconductor memory device, including a memory cell array, a control circuit which repeatedly perform an automatic erasure operation with respect to an entirety of the memory cell array, the automatic erasure operation including a preparatory write operation prior to an erasure operation and a following erasure operation, and a counter which counts how many times the automatic erasure operation is performed with respect to the entirety of the memory cell array, wherein the control circuit stops the automatic erasure operation in response to an event that the counter counts a desired number.
The nonvolatile semiconductor memory device as described above is provided with a function to automatically perform automatic erasure cycles as many times as desired to repeatedly carry out the preparatory write operation prior to an erasure operation and the following erasure operation. This function may be activated in response to a command input from an exterior of the device. This allows users or manufacturers to make the nonvolatile semiconductor memory device automatically perform the automatic erasure operations as many times as desired. Through this operation, the nonvolatile semiconductor memory device can be settled in a condition that exhibits a relatively short and stable erasure time compared to an initial erasure time.
Further, a method of erasing a nonvolatile semiconductor memory device according to the present invention includes the steps of starting a predetermined operation in response to a predetermine signal input from an exterior of said device and continuing the predetermined operation, said predetermined operation repeatedly performing an automatic erasure operation with respect to an entirety of a memory cell array, counting a number as to how many times the automatic erasure operation is performed, and stopping the predetermined operation in response to an event that the counted number reaches a predetermined number.
REFERENCES:
patent: 5138580 (1992-08-01), Farrugia et al.
patent: 5675546 (1997-10-01), Leung
patent: 5751944 (1998-05-01), Roohparvar et al.
patent: 0 681 295 (1995-11-01), None
patent: 2000040400 (2000-02-01), None
Tanuma Yasuhiko
Yoneda Takayuki
Lebentritt Michael S.
Nguyen Van-Thu
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