Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2000-08-25

2001-06-05

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240

Reexamination Certificate

active

06243290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrically rewritable nonvolatile semiconductor devices, particularly to nonvolatile semiconductor memory devices with memory cells for storing multilevel data.
2. Description of the Related Art
The number of cells of a semiconductor memory device made so as to be capable of storing N bits per cell by setting three or more threshold voltages for programming per cell can be reduced to 1/N of a semiconductor device capable of storing one bit per cell. The number of states of threshold voltages in which a cell of such memory device is placed shall satisfy the condition K=2
N
. An example of distribution of threshold voltages for programming data into memory cells to store two bits (N=2) per cell is shown in FIG.
59
. Here, four states of threshold voltages, zero state through third state are set, because K=4, and three voltages V pref
1
through V pref
3
are used to identify the first through third states of threshold voltages.
It is usually difficult for such multilevel memory device to reach the states of the threshold voltages shown in
FIG. 59
by one programming in view of precision. Thus, such a programming method is used that verification is executed as to whether the expected threshold voltage state for programming is gained after programming is executed; if programming is insufficient, programming is executed again; and programming and verification are repeated until the predetermined threshold voltage state has been reached. For example, for a memory device wherein data is programmed into a cell by injecting electrons into the floating gate of the cell, the quantity of charge at the floating gate is gradually increased by injecting a small amount of electrons into the floating gate each time programming is repeated and programming is continued until a predetermined quantity of charge has been gained at the floating gate, that is, the memory cell has reached the threshold voltage state for programming (storing) the data.
FIG. 60
shows examples of voltages that are applied to a word line (the control gate of a memory cell) when the above programming steps are taken. When programming is executed, a high voltage (bias) is applied to the word line and a programming bias voltage lower than the bias applied to the word line is applied to a bit line (the drain of the memory cell). When verification is executed, voltages V prf j (j=1, 2, . . . , K−1) required to verify whether programming is complete are applied. In this example, the word line voltage gradually increases during programming as the programming cycle advances and the programming data level changes, thereby increasing the quantity of electrons injected per application of the programming bias.
Because a complex circuitry is required to control the quantity of electrons injected as described above, a method in which the word line voltage is set constant and a simple circuitry is configured is often used. In this case, more programming and verification cycles are necessary, particularly in a case where a high threshold voltage is used for programming data.
A previous programming and verification scheme is known; for example, the one disclosed in Japanese Patent Prepublication No. Hei 9-180471, which will be referred to as a first scheme hereinafter. In relation to this scheme,
FIG. 59
shows distribution of threshold voltages for memory cells capable of storing information of two bits per cell,
FIG. 60
shows the relation between the voltage of selected word line and programming verify actions, and
FIG. 61
shows a flowchart of the process thereof. In the distribution of threshold voltages shown in
FIG. 59
, data is erased in the zero state of threshold voltage.
This first scheme is characterized in that programming of multilevel programming data is completed sequentially from one level to another level. First, for memory cells to be programmed in the first state of threshold voltage, first threshold level programming verification is executed. After the completion of the programming in the first state, for memory cells to be programmed in the second state of threshold voltage, second threshold level programming and verification are executed. After the completion of the programming in the second state, for memory cells to be programmed in the third state of threshold voltage, third threshold level programming and verification are executed. When programming in the third state is complete, the programming on all levels of threshold voltages terminates. In this scheme, threshold voltages are controlled with high precision because programming is completed by repeating programming action to program data into memory cells by applying bias to word and bit lines (programming bias application action) and verify action until the memory cells have reached a desired state of threshold voltage. However, sequential operation of precise threshold voltage control per level requires a great number of cycles of programming and verification, and consequently, long programming time is inevitable.
Another previous programming and verification scheme is also known, for example, the one disclosed in Japanese Patent Prepublication No. Hei 4-57294, which will be referred to as a second scheme hereinafter. The second scheme is characterized in that simultaneous programming of multilevel data is executed and verification procedure starts upon the completion of programming. Because of simultaneous programming and verification for multilevel data, in the second scheme, verification cycles can be decreased and programming time can be reduced.
In the programming verification procedure of the second scheme, as shown in
FIG. 62
, a memory cell current is compared with a plurality of reference currents and thereby programming on threshold voltage level is verified. When a constant voltage is applied to the bit line of memory cells, the current flow through the memory cells differs, depending on the threshold voltage of the memory cells. Then, current I cell flowing through a target memory cell
1
for verification is compared with currents I ref
1
through I ref
3
flowing through a reference cell array R and difference between both is detected by detectors SA
1
through SA
3
. A logic circuit LC executes arithmetic operation of the result of detection and outputs programming data level as D
1
and D
2
of two bits. This second scheme uses current sense amplifiers.
However, this scheme has the following natures. (1) Generating a plurality of reference current levels with precision is difficult in limited circuitry and the size of circuit structure becomes larger. (2) Because current sense amplifiers consume large current during current sensing operation, simultaneous verification for many memory cells is difficult and the programming throughput is limited. (3) Amplifiers of high sensitivity are required to verify multilevel data programming by using memory cell currents, which results in increased chip area. Therefore, the second scheme is not used in a case where a high programming throughput is especially required.
Another current sense amplifier example shown in
FIG. 63
is disclosed in Japanese Patent Prepublication No. Hei 10-241373. In this example, a single reference level I ref is used and memory cell current I cell flowing through a cell when bias voltage (WL voltage) on the word line is gradually increased in steps is compared with the reference level I ref. A timing detector TD detects timing when the memory cell current I cell becomes greater than the reference level I ref and thereby verification of programming is performed.
In this example, stepwise transition of the word line voltage is required in accordance with threshold voltage levels for programming and thus this requires longer verification than verification in the scheme shown in FIG.
62
. However, because verification can be performed by using a single reference level, the circuitry size can be reduced. Nevertheless, because current sense amplifie

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