Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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36518901, G11C 1140, G11C 1124

Patent

active

053495535

ABSTRACT:
A nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors having a lamination gate structure are arranged in a matrix manner at the position where a word line and a bit line cross each other. A lower voltage than a threshold voltage is applied to the word line selected at the time of a reading mode in a state that no electrical charge is stored in the floating gate.

REFERENCES:
patent: 5136533 (1992-08-01), Harari
"1991 International Electron Devices Meeting Technical Digest", pp. 11.4.1 through 11.4.4

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