Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1994-11-30

1997-01-21

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

257314, 257316, 257317, 257318, 257370, G11C 1134

Patent

active

055965296

ABSTRACT:
A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.

REFERENCES:
patent: 4794562 (1988-12-01), Kato et al.
patent: 5066992 (1991-11-01), Wu et al.
patent: 5282161 (1994-01-01), Villa
The 13th Annual IEEE Nonvolatile Semiconductor Workshop, J. Noda et al., "A Novel EEPROM Cell for High Density Application and Single Power Supply Power Operation", Feb. 20-22, 1984.
IEDM Tech. Dig., pp. 26-29, 1988, R. Shirota et al., "An Accurate Model of Subbreakdown Due to Band-to-Band Tunneling and Its Application".
IEDM Tech. Dig., pp. 24-27, 1981, J. R. Yeargain et al., "A High Density Floating-Gate EEPROM Cell".

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