Static information storage and retrieval – Floating gate – Particular biasing
Patent
1987-05-07
1988-02-16
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
365104, 365189, G11C 1140
Patent
active
047259833
ABSTRACT:
A nonvolatile random access memory comprising a memory cell including a first MOS transistor having a drain connected to a bit line and a gate connected to a word line, a memory transistor having a drain connected to a source of the first MOS transistor, a control gate connected to a first control signal line and a floating gate for storing charges, and a second MOS transistor connected between a source of the memory transistor and a ground potential and connected to a second control signal line. The memory cell operates as a random access memory cell when the first control signal line is an "H" level and the second MOS transistor is turned off in response to and "L" level on the second control signal line, and operates as an EEPROM when the first control signal line is an "L" level and/or a "V.sub.p " level.
REFERENCES:
patent: 4661833 (1987-04-01), Mizutani
ISSCC Digest of Technical Papers, Feb. 24, 1983, "Nonvolatile Memory" by Neil J. Becker et al.
Fears Terrell W.
Garcia Alfonso
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Nonvolatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2224804