Nonvolatile semiconductor memory device

Static information storage and retrieval – Magnetic bubbles – Guide structure

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357 231, 357 2314, 365185, H01L 2978, H01L 2710

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active

046300872

ABSTRACT:
In a nonvolatile semiconductor memory device having a matrix of electrically erasable and programmable memory cells each of which has a floating gate, an erase gate, and two control gates, a relationship among the potentials selectively applied to the floating gate, the erase gate, and the two control gates is preset to decrease changes in the threshold level of the half-selected memory cells, thereby achieving high reliability. In the writing mode, a voltage of +25 V is applied to the selected row and column control lines, a first low voltage of 0 V is applied to the remaining row and column control lines, and a second low voltage of +5 V is applied to a source control line. In the erasing mode, a low voltage of 0 V is applied to the selected row and column control lines, a first high voltage of +25 V is applied to the remaining row and column control lines, and a second high voltage of +20 V is applied to the source control line.

REFERENCES:
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
patent: 3825946 (1974-07-01), Frohman-Bentchkowsky
patent: 4477883 (1984-10-01), Wada
patent: 4503519 (1985-03-01), Arakawa
IEEE Trans. Elec. Dev., vol. ED-23, No. 4, Apr. 1976, "Electrically Alterable . . . Structure", Iizuka et al., pp. 379-387.

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