Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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36518529, G11C 800

Patent

active

061479098

ABSTRACT:
It is an object of the invention to provide an EEPROM, in which the third positive potential for erase verify is supplied from a negative potential generating circuit for supplying a negative or ground potential to a word line. The EEPROM is composed of a P potential supply circuit for respectively supplying a potential to sources of P channel transistors in invertors, which are respectively connected with word lines, a N potential supply circuit for respectively supplying a potential to sources of N channel transistors in the invertors, a read/write decision circuit for deciding whether the EEPROM operates in a read or write mode, and an erase decision circuit for deciding whether the EEPROM operates in an erase mode or not.

REFERENCES:
patent: 5680349 (1997-10-01), Atsumi

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