Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

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Details

36518519, 36518524, 36518529, 365218, G11C 1604

Patent

active

058703349

ABSTRACT:
In a nonvolatile semiconductor memory device including a memory cell array obtained by arranging, in a matrix manner, electrically programmable memory cells, each of which comprises stacking a charge storage layer and a control gate on a semiconductor layer through an insulating film, the threshold voltages of the memory cells are detected after erasing, and data are programmed in a fast programmable cell at a relatively low voltage and in a slow programmable cell at a relatively high voltage, thereby suppressing variations in threshold voltages after programming within the same period of programming time.

REFERENCES:
patent: 5278794 (1994-01-01), Tanaka et al.
patent: 5652719 (1997-07-01), Tanaka et al.

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