Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

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Details

36518512, 36518517, 36518518, 36518524, G11C 1600

Patent

active

057814783

ABSTRACT:
There is provided a non-volatile semiconductor memory device comprising: a memory cell array in which a plurality of memory cell units are arranged in a matrix form, the memory cell units each having a memory cell section and one or a plurality of select MOS transistors, the memory cell having one or a plurality of non-volatile memory cells, and the select MOS transistors allowing the memory cell section to be electrically conducted to a common signal line, wherein one end of each of the memory cell units is connected to a first common signal line in a state that the plurality of 2n (n.+-.2) memory cell units, sharing a word line, have a contact in common; and the other end of each of the memory cell units is connected to a second common signal line in a state that n memory cell units, sharing a word line and having no contact in common at one end of the memory cell unit, have a contact in common, and n memory cell units, sharing a contact at one end of the memory cell unit, have a contact in common.

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