Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1996-02-23

1999-04-06

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518506, 36518521, 36523003, 365203, G11C 1604

Patent

active

058927131

ABSTRACT:
The memory mat is divided in two banks, which share the sense & latch circuit. As an example of the circuit operation, the information contained in the memory cells in a block of four bit lines BL11a-BL14a connected to a word line WL1a in the memory array MAa of the bank A is temporarily stored in the sense & latch circuits SL11-SL14. The information of bit lines is latched to the sense & latch circuit SLa through the sub-input/output signal lines IO1a and IO2a by the switches YS1a and YS2a that alternately operates at a cycle two times that of the external clock. The latched information is then output onto the input/output signal line IOa by the switch SWa in synchronism with the clock. After the four bit lines BL11a-SB14a have been read out, the sense & latch circuits SL11-S114 in that block are reset and the bit lines on the bank B are precharged while the information on the bank A is being output. After the reading on the bank A is finished, the word line on the bank B is raised to a high level to execute the read operation in the similar manner. In this way, the word lines on the two banks are alternately raised to the high level for continuous and alternate reading. This configuration provides a nonvolatile semiconductor memory device which allows high-speed block reading.

REFERENCES:
patent: 5014246 (1991-05-01), Uomatsu et al.
patent: 5262992 (1993-11-01), Uondou
patent: 5267214 (1993-11-01), Fujishima et al.
patent: 5280447 (1994-01-01), Hazen et al.
patent: 5301162 (1994-04-01), Shimizu
patent: 5315555 (1994-05-01), Choi
patent: 5557568 (1996-09-01), Miyamoto et al.

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