Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-09-10
2000-12-05
Hoang, Huan
Static information storage and retrieval
Floating gate
Particular biasing
36518521, 36518522, G11C 1604
Patent
active
061575763
ABSTRACT:
Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.
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Kubota Yasurou
Kume Hitoshi
Muto Tadashi
Seki Koichi
Shoji Kazuyoshi
Hitachi , Ltd.
Hitachi ULSI Engineering Co., Ltd.
Hoang Huan
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