Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2009-08-07

2011-12-13

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185250

Reexamination Certificate

active

08077525

ABSTRACT:
A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word lines configured to commonly connect control gates of the memory cells. A data erase operation is executed by first applying a pre-charge voltage to the word lines, then setting to a floating state the word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to the word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where the memory cell array is formed, thereby altering a threshold voltage of the memory cells in the selected block.

REFERENCES:
patent: 6477088 (2002-11-01), Ogura et al.
patent: 6967874 (2005-11-01), Hosono
patent: 2008/0181019 (2008-07-01), Shibata
patent: 2005-25824 (2005-01-01), None
patent: 2005-25891 (2005-01-01), None
patent: 2006-252624 (2006-09-01), None
patent: 2007-250187 (2007-09-01), None
Decision of Refusal issued Mar. 8, 2011, in Japanese Patent Application No. 2008-238266 (with English translation).
Office Action issued Nov. 9, 2010, in Japan Patent Application No. 2008-238266 (with English translation).

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