Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185050, C365S185270, C365S063000

Reexamination Certificate

active

08059462

ABSTRACT:
The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire connected to a cell well line of a memory cell, a third wire which supplies a power supply voltage to a circuit arranged outside of a region of the cell array, a fourth wire and a fifth wire being arranged in a row direction within the cell array region, and the first wire, the second wire and the third being formed in a layer above a layer in which the bit line within the cell array is formed, the fourth wire and the fifth wire being formed in the layer in which the bit line within the cell array region is formed.

REFERENCES:
patent: 5591999 (1997-01-01), Momodomi et al.
patent: 7221017 (2007-05-01), Forbes et al.
patent: 7286403 (2007-10-01), Maejima
patent: 2006/0002216 (2006-01-01), Ooishi
patent: 2006/0198196 (2006-09-01), Abe et al.
patent: 2008/0031048 (2008-02-01), Jeong et al.
patent: 2008/0186766 (2008-08-01), Ogura et al.
patent: 2009/0027941 (2009-01-01), Maejima et al.
patent: 2006-245547 (2006-09-01), None
patent: 2006-302960 (2006-11-01), None

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