Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185010, C365S185330

Reexamination Certificate

active

07623380

ABSTRACT:
A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.

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Richard J. McPartland, et al., “1.25 Volt, Low Cost, Embedded Flash Memory for Low Density Applications”, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 158-161.

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