Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2007-02-02

2008-08-12

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185270

Reexamination Certificate

active

07411834

ABSTRACT:
A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.

REFERENCES:
patent: 5311479 (1994-05-01), Harada
patent: 6207998 (2001-03-01), Kawasaki et al.
patent: 6865114 (2005-03-01), Pio
patent: 2007/0297236 (2007-12-01), Tokiwa
patent: 2008/0043538 (2008-02-01), Sugawara
patent: 2001-28428 (2001-01-01), None
patent: 2003-141887 (2003-05-01), None
patent: 2004-185660 (2004-07-01), None
patent: 2005-243211 (2005-09-01), None

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