Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518511, 36518517, G11C 1604

Patent

active

060317647

ABSTRACT:
A nonvolatile semiconductor device comprises a memory cell array with, for example, NAND memory cells, a row decoder for selecting and driving word lines, and data sense amplifier/latch circuits for exchanging data with the selected memory cells via bit lines. The memory cell array is divided into blocks in the direction of word line. The individual blocks are formed in wells formed separately in a semiconductor substrate. Each word line driven by the row decoder is provided continuously by means of control transistors formed in the boundary areas between blocks. Turning off the control transistors enables the data to be erased simultaneously block by block.

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