Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2005-12-20

2005-12-20

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189090

Reexamination Certificate

active

06977861

ABSTRACT:
The present invention provides a nonvolatile semiconductor memory device capable of achieving the speeding-up of reading and a reduction in layout area. A control gate electrode of each of memory cell transistors employed in the nonvolatile semiconductor memory device according to the present invention is configured so as to be capable of assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential upon its operation. A second NMOS transistor is provided between the gate of a first NMOS transistor that drives a control gate electrode (WL) to the first power supply potential (VCC) and a control signal (/ER) connected to the gate thereof. The source of the second NMOS transistor is inputted with the control signal (/ER) and the drain thereof is connected to the gate of the first NMOS transistor. A PMOS transistor is provided in parallel with the first NMOS transistor. A transfer gate comprising these NMOS and PMOS transistors drives the control gate electrode (WL).

REFERENCES:
patent: 5394374 (1995-02-01), Ishimura et al.
patent: 5959890 (1999-09-01), Yamamoto et al.
patent: 6373745 (2002-04-01), Saito et al.
patent: 07-182860 (1995-07-01), None
patent: 07-192474 (1995-07-01), None

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