Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2003-02-21

2004-06-15

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185170, C365S189050, C365S189070

Reexamination Certificate

active

06751122

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2002-316719, filed Oct. 30, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device. More specifically, the present invention relates to an integrated circuit chip in which initialization is performed by using a ROM Fuse.
2. Description of the Related Art
Integrated circuit chips (IC chips) such as NAND type EEPROM having a electrically programmable nonvolatile semiconductor memory have increasingly employed a ROM fuse for an initial setup operation (for example, see Japanese Patent Application No. 2001-176290). The ROM Fuse is a predetermined data region
101
a
on a memory cell array (or dedicated memory)
101
, in which various initial setup values required for initializing an IC chip are stored, as shown in FIG.
12
. The various initial setup values stored in the predetermined data region
101
a
are automatically read by a sense amplifier (S/A)
105
immediately when the power-on of the IC chip is detected by a control circuit
103
.
The various initial setup values read out from a ROM Fuse are then transferred to individual registers (data latch circuits)
107
a
,
107
b
, and
107
c
and stored therein. The various initial setup values stored in individual registers
107
a
,
107
b
, and
107
c
are respectively sent to the corresponding circuits. For example, the initial setup values for setting up a write voltage and erase voltage stored in the register
107
c
are sent to a high-voltage generation circuit
109
. In this manner, the initial setup operation (initialization) of the IC chip is performed. The ROM Fuse is advantageous since the design can be made with a high degree of freedom compared to conventional fuses such as a laser-melt type fuse and the cost for a test run can be saved. Accordingly, the demand for the ROM Fuse has recently increased.
However, since initial setup values are actually written in memory cells in the form of data in a ROM Fuse, the reliability of data is lower than those of conventional fuses. To overcome the low reliability, the following method has been contemplated.
For example, not a single set of initial setup data but several sets thereof are stored in a ROM Fuse and the initial setup data of individual sets are compared at power-on. If this method is employed, the reliability of data can be improved.
As explained above, the reliability of data in a ROM Fuse can be improved by comparing several sets of initial setup data. However, there is a possibility that data gets garbled. It is also considered that all initial setup data of each set may be put in a FAIL status. More specifically, in the initial setup operation, since data is read out when power is turned on, the readout data greatly varies depending upon the state of power. Consequently, it is sometimes impossible to correctly read out the initial setup data. In such a case, effective initial setup data cannot be set during the initial setup operation. This inevitably means the initialization of the IC chip is incomplete. For example, defective cells have not been replaced for redundancy and the trimming of power has not been performed.
When the initialization is not effectively made not only a normal memory operation of an IC chip cannot be ensured but also disappearance of valuable cell data and destruction of memory cells themselves may occur. Accordingly, it has been desired to develop an effective means for protecting an IC chip from the disappearance of cell-data and so forth even when the initial setup operation is not successfully completed by failure of the initial setup operation.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, these is provided a nonvolatile semiconductor memory device, comprising a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written; a detection circuit which detects turn-on of power; a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit; a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective; and a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.


REFERENCES:
patent: 5345413 (1994-09-01), Fisher et al.
patent: 6052313 (2000-04-01), Atsumi et al.
patent: 6462985 (2002-10-01), Hosono et al.
patent: 6646930 (2003-11-01), Takeuchi et al.
patent: 2001-176290 (2001-06-01), None
U.S. patent application Ser. No. 09/731,910, Hosono et al., filed Dec. 8, 2000.
U.S. patent application Ser. No. 10/185,645, Nakamura et al., filed Jun. 28, 2002.
U.S. patent application Ser. No. 10/302,771, Imamiya, filed Nov. 21, 2001.

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