Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2003-01-24

2004-07-27

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185220

Reexamination Certificate

active

06768676

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, in particular, a nonvolatile semiconductor memory device employing a multi-valued write method using channel hot electrons.
Conventionally, as a most commonly used nonvolatile semiconductor memory device, flash memory of an ETOX (EPROM Thin Oxide, a registered trade name of a product of Intel Corporation) type can be mentioned.
FIG. 8
is a schematic cross sectional view showing a memory cell of this ETOX-type flash memory. As shown in
FIG. 8
, a floating gate
64
is formed on a substrate
60
on which a source
61
and a drain
62
are formed with a predetermined gap therebetween and a region between the source
61
and the drain
62
via a tunnel oxide film
63
, and a control gate
66
is further formed on the floating gate
64
via an interlayer insulating film
65
.
An operation principle of this ETOX-type flash memory is described below. As shown in Table 1 as voltage conditions, at the time of a write operation, a write voltage Vpp (for example, 9 V) is applied to the control gate
66
, a standard voltage Vss (for example, 0 V) is applied to the source, and a voltage of 5 V is applied to the drain
62
.
TABLE 1
Control
gate
Drain
Source
Substrate
Write
  9 V
5 V/open
0 V
0 V
Erase
−9 V
Open
6 V
0 V
Read
  5 V
1 V
0 V
0 V
It is noted that the drain
62
of a memory cell to which data is not written is opened. Consequently, a large amount of current flows in a channel layer, hot electrons are generated in a portion on the drain side where an electric field is high, electrons are implanted into the floating gate
64
, and a threshold voltage of the memory cell is raised.
FIG. 9
shows a state of threshold voltages of two-valued flash memories. The right side of
FIG. 9
is a distribution state of threshold voltages in a program (written) state with data “0”.
Furthermore, at the time of an erase operation, Vnn (for example, −9 V) is applied to the control gate
66
, Vpe (for example, 6 V) is applied to the source
61
, and electrons are pulled from the floating gate
64
on the source side to lower a threshold voltage. The left side of
FIG. 9
is a distribution state threshold voltages in an erased state with data “1”. Upon this erase operation, a BTBT (Band To Band Tunneling) current flows from the source side to the substrate
60
. When this current is generated, hot holes and hot electrons are generated at the same time. Of these, the hot electrons flow to the drain
62
, but, on the other hand, the hot holes are pulled to the tunnel oxide film
63
side and trapped inside the tunnel oxide film
63
. Generally, this trap is considered to deteriorate reliability.
Furthermore, at the time of a read operation, 1 V is applied to the drain
62
, and 5 V is applied to the control gate
66
. When a memory cell is in an erased state and the threshold voltage is low, a current flows through the memory cell, and data “1” is determined. On the other hand, when a memory cell is in a program state and the threshold voltage is high, a current does not flow through the memory cell, and data “0” is determined.
Meanwhile, recently, multi-valued techniques are being developed for the purpose of lower costs.
FIGS. 10A
to
10
D are conceptual diagrams showing a state electrons in a floating gate in the case of a four-valued flash memory using the multi-valued technique (the one shown in
FIG. 10
is a four-valued one, while
FIG. 11
shows a two-valued one for comparison). As shown in
FIG. 10
, a state at each level is determined by the number of electrons in the floating gate. The state of the threshold voltage in this case is divided into four threshold voltage levels as shown in
FIG. 12
as follows.
Data “00”: threshold voltage of 5.7 V or higher
Data “01”: threshold voltage of 4.7-5.0 V
Data “10”: threshold voltage of 3.7-4 V
Data “11”: threshold voltage of 3.0 V or lower
Such a state of the threshold voltage is adjusted by controlling the amount of electrons to be implanted into the floating gate by utilizing a characteristic that the threshold voltage is changed by the number of electrons in the floating gate shown in FIG.
10
.
A point of this multi-valued technique is how the threshold voltage (in particular, threshold voltages for data “01” and data “10”, which are intermediate levels) is made within a predetermined threshold voltage.
Procedures of this multi-valued technique are described below. A general write method is disclosed in Japanese Patent Laid-Open Publication No. 2001-57091 and IEEE J. Solid-State Circuits, Vol. 35, No. 41, pp. 1655-1667, November, 2000, “40 mm
2
3 V Only 50 MHz 64 Mb 2 b/cell CHE NOR Flash Memory”. The method described in these references includes procedures in which program (write) pulse application and a verify operation for verifying a threshold voltage of a memory cell after program pulse application are repeated, and the drain of a memory cell of which threshold voltage reaches a predetermined threshold voltage is opened in subsequent program pulse application so that a drain voltage is not applied thereto, while 5 V is applied to the drain of a memory cell of which threshold voltage does not reach the predetermined threshold voltage, and a program pulse is applied to continue a write operation. When threshold voltages of all memory cells to be programmed (written) finally reach the predetermined threshold voltage, the write operation is terminated.
In particular, a procedure is described in which a voltage applied to the control gate is set to be low at the time of a first program (write) operation and the voltage of the control gate is raised by a certain voltage for each program pulse application in order to increase a program (write) speed in this case.
FIG. 13
shows a write algorithm in this case.
As shown in
FIG. 13
, when a program is started, N is set at zero in step S
1
, and a verify operation is performed in step S
2
to determine whether a threshold voltage of a memory cell is 3.7 V or higher. Then, when the threshold voltage of the memory cell is lower than 3.7 V, N is increased by an increment (N+1) in step S
3
. The operation proceeds to step S
4
, and a gate voltage Vg (=Vg10) is raised by &Dgr;Vg×(N−1). In step S
5
, a write pulse having a voltage of Vg+&Dgr;Vg×(N−1) is applied to the control gate. Then, the operation returns to step S
2
, and steps S
2
to S
5
are repeated until the threshold voltage of the memory cell becomes 3.7 V or higher.
On the other hand, when the threshold voltage of the memory cell is 3.7 V or higher in step S
2
, the operation proceeds to step S
11
, and N is set at zero. A verify operation is performed in step S
12
to determine whether the threshold voltage of the memory cell is 4.7 V or higher. Then, when the threshold voltage of the memory cell is lower than 4.7 V, N is increased by an increment (N+1) in step S
13
. The operation proceeds to step S
14
, and the gate voltage Vg (=Vg01) is raised by &Dgr;Vg×(N−1). In step S
15
, a write pulse having a voltage of Vg +&Dgr;Vg×(N−1) is applied to the control gate. Then, the operation returns to step S
12
, and steps S
12
to S
15
are repeated until the threshold voltage of the memory cell becomes 4.7 V or higher.
On the other hand, when the threshold voltage of the memory cell is 4.7 V or higher in step S
12
, the operation proceeds to step S
21
shown in
FIG. 14
, and N is set at zero. A verify operation is performed in step S
22
to determine whether the threshold voltage of the memory cell is 5.7 V or higher. Then, when the threshold voltage of the memory cell is lower than 5.7 V, N is increased by an increment (N+1) in step S
23
. The operation proceeds to step S
24
, and the gate voltage Vg (=Vg00) is raised by &Dgr;Vg×(N−1). In step S
25
, a write pulse having a voltage of Vg +&Dgr;Vg×(N−1) is applied to the control gate. Then, the operation returns to step S
22
, and

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