Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-03-11
2003-04-08
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185170, C365S189020
Reexamination Certificate
active
06545909
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electrically erasable programmable read-only memory (EEPROM) device, and more particularly to an EEPROM storing data of a multilevel.
The present application is based on Japanese Patent Application. No. 8-61352, Japanese Patent Application. No. 8-61443, Japanese Patent Application. No. 8-61444 and Japanese Patent Application. No. 8-61449, the content of which is incorporated herein by reference.
As one of a means for increasing the capacity of an EEPROM, a multilevel storing EEPROM has been known capable of causing n (n≧3)-level information to be stored in one memory cell. A four-level data storing structure is arranged such that each cell is provided with one of four threshold voltages and the threshold voltages correspond to 2-bit information expressed as “0, 0”, “0, 1”, “1, 0” and “1, 1”.
To read data in the memory cell in which n-level information has been stored, data read from the cell must be compared with (n−1) reference voltages. Accordingly, (n−1) sense amplifiers have been required (refer to, for example, Japanese Patent KOKAI Publication No. 61-117796). A four-level data storing EEPROM must have three sense amplifiers.
Therefore, the four-level data storing EEPROM involves the storing density in the memory cell being doubled as compared with the EEPROM having binary data storing cells. Although the area of the memory cells can be halved, the area of the sense amplifiers is tripled. Thus, a required high density structure cannot be formed. In particular, an EEPROM having a sense amplifier provided for each bit line for the purpose of page reading cannot easily be formed into a large capacity structure because the number of the sense amplifiers is enlarged excessively.
A read-only memory has been disclosed in Japanese Patent KOKAI Publication No. 62-54896 which is capable of decreasing the number of sense amplifiers by using an output from a sense amplifier, which has determined cell data, to control the reference voltages of other sense amplifiers. However, the foregoing structure cannot be applied to a writable memory.
On the other hand, a multilevel data storing EEPROM for causing n (n≧3) types of threshold voltages to be stored in the memory cells must distribute the threshold voltages in each of narrow ranges when data to be stored is written. Therefore, writing is performed little by little and whether or not data has been written in each memory cell within a required threshold voltage range is verified between writing operations. If a cell, in which data has not sufficiently been written, exists, additional writing of the cell has been performed. The foregoing technology is arranged to cause optimum writing to be performed for each memory cell and is known as “bit-by-bit verification”. The concept of the bit-by-bit verification has been disclosed in Japanese Patent KOKAI Publication No. 3-295098.
The technology disclosed in Japanese Patent KOKAI Publication No. 3-295098 relates to a binary-data storing EEPROM. The bit-by-bit verification applicable to a multilevel data storing EEPROM has been disclosed in Japanese Patent KOKAI Publication No. 7-93979. However, the apparatus disclosed in Japanese Patent KOKAI Publication No. 7-93979 requires (n−1) sense amplifiers and (n−1) verify circuits. Although the memory cell is able to store larger quantity of data and thus a large quantity of data can be stored in a chip having the same area, the size of a circuit for controlling data read/write is enlarged excessively to form a highly integrated structure.
Moreover, the multilevel-data storing EEPROM involves the number of bits of signals for use therein, in particular, the signals for use in the input/output data line being different from the number of bits of signals for use in a circuit substrate for establishing the connection between the multilevel-data storing EEPROM with another integrated circuit apparatus, such as a processor. As a result, the multilevel-data storing EEPROM must have a circuit for converting the number of bits of the signal for use in the outside portion of the apparatus into the number of bits of the signal for use in the apparatus.
When the number of multilevel data is n (n is a natural number not smaller than 3) in the conventional multilevel-data storing EEPROM having the verify means, (n−1) verify circuits must be provided. Therefore, also (n−1) sense amplifiers and (n−1) data latches must be provided to correspond to the verify circuits. As a result, the size of the circuit connected to the bit line, that is, the size of the column-system circuit, in particular, the number of the sense amplifiers and data latches cannot be reduced. Thus, a highly integrated structure cannot be realized.
Moreover, the circuit for converting the number of bits of the signal for use in the outside portion of the apparatus and the number of bits of the signal for use in the apparatus must be provided. Therefore, a highly integrated structure cannot be realized and a high speed input/output operation cannot be performed.
A nonvolatile semiconductor memory device according to an aspect of the present invention comprises: a memory cell array in which memory cells storable multilevel data are arranged in a matrix; bit line controllers having latch circuits configured to latch write data and sense circuits configured to sense read data, and bit lines which connect the bit line controllers and the memory cells, the bit lines supplying write data from the latch circuits to the memory cells during data write mode and supplying read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.
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Ohuchi Kazunori
Takeuchi Ken
Tanaka Tomoharu
Tanzawa Toru
Foley & Lardner
Le Vu A.
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